All-
I'm using Spartan 3 + XST 7.1sp4. In the code below, is there a way to use a combinatorial always block and a for-loop to make it more readable and not take 32 lines of source?
-Jeff
wire [31:0] a; reg [7:0] b [31:0]; reg [2:0] bit;
assign a = { b[31][bit], : : b[10][bit], b[9][bit], b[8][bit], b[7][bit], b[6][bit], b[5][bit], b[4][bit], b[3][bit], b[2][bit], b[1][bit], b[0][bit] };
This should work:
integer i; always @* for( i=0; i
Thanks John...
XST complains that a is a wire.
-Jeff
Sorry...
reg [31:0] a; reg [7:0] b [31:0]; reg [2:0] bit; integer i; always @* for( i=0; i Thanks John...
John-
Well... I need a to be a wire. I guess there may not be a way to take advantage of for-loops with assign statements.
-Jeff
A doesn't need to be declared a wire to be a combinatorial value. Because the always block is a combinatorial block, the reg value is a combinatorial result, not implemented as a flip-flop or "register" primitive. The always constructs need reg-declared variables to work.
Change "a" to reg per above. Compile. Realize. Smile.
John-
Ok, got it. I suppose I can think of it as a latch, always enabled. But to let you know XST doesn't like the "*". To synthesize, I had to use:
always begin for (i=0; i
The "always @*" or "always @(*)" equivalent construct is a Verilog2001 catchall for the sensitivity list. If you don't choose Verilog2001 support (it's optional in the Synplify compiler) or if XST 7.1.04i doesn't support that construct, you would do best to include the full sensitivity list - "always @(b or bit)"
Also - since the "for" statement is a single statement, the begin/end constructs are superfluous; they do no harm but they add nothing. It's only when there are multiple lines that the begin/end are needed.
John-
Many thanks.
XST burps up "Unexpected event in always block sensitivity list." with that syntax.
Even going sans list, the result is still not equivalent to the lengthy assign statement. XST changes routing enough to add 1 nsec on a local clock net that I use as my canary.
Ya know. Sorry... I've been trying so many darn things I kept 'em there for experimenting.
-Jeff
*Never* count on a reference net for timing information to give you a clue on synthesis. Synthesizers will move things around and place & routes confuse things further. Only by checking the technology view post-synthesis will the "equivalence" be checked 100% to my satisfaction.
I hope this will work
wire [31:0] a; reg [7:0] b [31:0]; reg [2:0] bit; genvar i; generate for( i=0; iXST burps up "Unexpected event in always block sensitivity list." with
Also observed similar problem. Problem is that the Xilinx ISE is not accepting multidimnsional array in the sensitivity list. But it will work with synplify.
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