Field-Programmable Gate Arrays

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Static Timing Analysis vs Dinamic Timing Analysis

Hi!, Could anybody explain me these concepts and their differences?. And what is done in foundation ISE tool of xilinx?....
1 comments posted 19yrs
posted by jmunir
1 comments posted 19yrs posted by jmunir

Input setup time & Output valid delay

I am new in this field and I have been working with ISE Xilinx tool. When I want to create a testbench waveform I have...
1 comments posted 19yrs
posted by jmunir
1 comments posted 19yrs posted by jmunir

IDELAY Calibration - Virtex 4

I am working on a design that takes a source-synchronous LVDS bus (8 data bits + clock, SDR) at a high speed (250MHz) a...
4 comments posted 19yrs
posted by tjc-sda
4 comments posted 19yrs posted by tjc-sda

Re: PCB Design Houses

Matthew, I have a guy that I use on these types of jobs, but he is in California. We have done many multi-processor des...
0 comments posted 19yrs
posted by tjc-sda
0 comments posted 19yrs posted by tjc-sda

query in a design

I am design for an asic.prototyping a fpga I have four design file with 12 similar functional channels.Performance was...
1 comments posted 19yrs
posted by vsrpkumar
1 comments posted 19yrs posted by vsrpkumar

state problems with Quartus II 6

I have declared a state in VHDL like this: type state_type is ( state1, state2, state3, state4, state5, state6, state7,...
2 comments posted 19yrs
posted by fb
2 comments posted 19yrs posted by fb

PCMCIA interface

Hi everybody, A part of a project I'm designing is a PCMCIA bus card with a 32 bit data system bus. The system included...
7 comments posted 19yrs
posted by piclist9
7 comments posted 19yrs posted by piclist9

How could the 'Serial write time out' happen

I implemented an algorithm into fpga board. I wrote the Matrix data to FPGA board from Matlab and the result came back....
4 comments posted 19yrs
posted by threeinchnail
4 comments posted 19yrs posted by threeinchnail

pulse jitter due to clock

Hi to everyone, I'm developing some electronics to make a time measurement with a resolution of 25 ps. I'm using a dedi...
31 comments posted 19yrs
posted by alessandro.basili
31 comments posted 19yrs posted by alessandro.basili

ML405: Board support package

Hi, Can anyone provide me with a board support package for the ML405 board? In EDK 8.1 installation only ML401/402/403/4...
0 comments posted 19yrs
posted by gerd.van.den.branden
0 comments posted 19yrs posted by gerd.van.den.branden

FPGA board

Hi, all I need to have a pulse signal. His frequency is 12.5 Mhz but my problem is rise time. I would like to get a maxi...
1 comments posted 19yrs
posted by olive_dominguez
1 comments posted 19yrs posted by olive_dominguez

combinatorical divide by 2 in FPGA

Hi this may sound strange but I need flip flop or divide by 2 element that is made purely out of combinatorical logic a...
16 comments posted 19yrs
posted by Antti.Lukats
16 comments posted 19yrs posted by Antti.Lukats

Hpw to remove combinational loops in quartus s/w

I have some combinational loops in my design.2 blocks are there with interface .1 st block output is going to second on...
1 comments posted 19yrs
posted by vsrpkumar
1 comments posted 19yrs posted by vsrpkumar