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IDELAY Calibration - Virtex 4

I am working on a design that takes a source-synchronous LVDS bus (8 data bits + clock, SDR) at a high speed (250MHz) as the input off a cable. I will be using the XC4VLX15 part. I read in the databook about the IDELAY/IDELAYCTRL operation that can be used to account for package and routing skews. What I don't quite understand is the calibration process. I understand the timing (64 taps @ 78.125Mhz with non-accumulating error) and how an n-tap delay line works. I just don't understand how to calibrate a signal dynamically without an input signal being present. Since my data and clock source is external (and I have no idea when data will start) I don't understand how the calibration can take place. When the cable is idle, the clock line will toggle, but the data lines will all be static. (I do see that an idle pattern of FF-00-FF-00... could be handy). When the cable is not connected though everything will be 0 - even the clock. The other option seems to be the fixed delay approach - then I just need to use the static timing analyzer to account for the flight time and routing delays so that they all "line-up" right on the balls. The datasheet claims a maximum flight-time skew of 80ps for any pin in the device (+/- 1 on the tap count). Then, I just need to look up the PAD --> IDELAY.D, divide by

78ps and add 1 for each of the 8 data bits. Am I missing something?

I can't tell you how many times in my life I wished I could slide the clock or data to account for internal chip routing delays. Especially on pad to pad delay paths that went through a flip-flop.

This seems too good to be true - so I must be missing something.

Trevor Coolidge

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Trevor Coolidge
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Trevor Coolidge schrieb:

Hi Trevor,

the IDELAY calibrates against 200MHz clock. there is no need to have any of the IOs toggling or having any signal, all you need is 200MHz reference clock. In early xilinx docs this

200MHz was required to come directly from external source, but later it was relaxed so it is allowed to generat the 200MHz using a DCM.

Antti

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Antti

Thank you for the clarification.

Reply to
Trevor Coolidge

The Idelays can be adjusted at any time once the 200 MHz reference clock is present, however that adjustment just allows you to increment or decrement the delay in 75ps increments. Your training state machine normally should use one of the externally applied signals (clock or data) as a reference to set the delay. Typically, you'd adjust the delay to first find the edges in the incoming signal, then set the delay midway between the edges so that you are centered in the eye. You need the external signal present and switching on every clock cycle in order to do this type of training. If you've got an incoming clock at the same frequency as a clock in the FPGA but at an unknown phase, you can use that incoming clock as the reference (This is the case with QDR memory, for example). If there is not an incoming clock, you may need a training pattern on the data lines to force an alternating 1 -0 pattern to train against.

Reply to
Ray Andraka

Ray Andraka schrieb:

correct I was refererring to IDELAYCTRL that is used to calibrate the IDELAY taps to be constant over temperature and process this only requires the 200MHz to present.

to actually calibrate the IDELAYs some signal is required on each IOs to compare against with.

Antti

Reply to
Antti

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