Field-Programmable Gate Arrays

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Spartan 3/3E to Standard TTL/Low power devices

What would you guys recomend as a bus transciever for interfacing with standard TTL and low power TTL logic? I'm thinki...
4 comments posted 19yrs
posted by grant
4 comments posted 19yrs posted by grant

Validity of data on rising edge of clock

It seems to be annoying to have my data valid on the rising edge of a clock internal to the FPGA. If I have a process t...
3 comments posted 19yrs
posted by lloyd.rochester
3 comments posted 19yrs posted by lloyd.rochester

Warnings in Xilinx 8.2i

I am new to CPLD's and I am trying to make a new design incorporating some of the old abel code. I am using schematic e...
10 comments posted 19yrs
posted by learnfpga
10 comments posted 19yrs posted by learnfpga

Maximum Operating Frequency

Hi On what factors the maximum operating frequency of ahb master and slave depends ? in general what is the maximum freq...
1 comments posted 19yrs
posted by tera.bits
1 comments posted 19yrs posted by tera.bits

Synthesis size of Circuits?

Hi, I am a student, without much experience of synthesis. My task was to make some modifications (i.e. insert faults) t...
8 comments posted 19yrs
posted by olson_ord
8 comments posted 19yrs posted by olson_ord

V-5 power saving ...how?

Hello! I'm trying to design in a V5, which will be sharing a memory bus with a DSP and some peripherals. However, the V...
1 comments posted 19yrs
posted by jonas
1 comments posted 19yrs posted by jonas

use boundary scan in spartan-3

Hi all, i'm new to boundary scan and want to make it work in the xilinx starter board, which contains a spartan-3 FPGA...
7 comments posted 19yrs
posted by florent.peyrard
7 comments posted 19yrs posted by florent.peyrard

Compiling Linux Kernel for ML405

Dear all, I'm trying to build a straightforward Linux Kernel for the Xilinx ML405 board and I'm running into one small...
4 comments posted 19yrs
posted by petermendham
4 comments posted 19yrs posted by petermendham

ise 7.1

i'm trying to install ise 7.1 on solaris 10 running on parallels VM. Setup quits after the following meesages: /tmp/win...
0 comments posted 19yrs
posted by ahb3
0 comments posted 19yrs posted by ahb3

USB and AHB

Hi I am very new to usb, I have some basic questions reagarding usb with ahb . Suppose i have a ahb structure like 2 ma...
5 comments posted 19yrs
posted by tera.bits
5 comments posted 19yrs posted by tera.bits

Problems with Opencores' I2C "READ" function

Hello, I am wondering if any of you have encountered a problem in which the Opencores' I2C "READ" function failed. The...
2 comments posted 19yrs
posted by markus_1401
2 comments posted 19yrs posted by markus_1401

8080 FSGA model in an FPGA

I would like to eventually make an 8080 out of Field Solderable Gate Arrays. ;) (trasistors) First, I want to design th...
34 comments posted 19yrs
posted by grant
34 comments posted 19yrs posted by grant

Xilinx 2 DCMs with delay on lock

Hio folks, I'm trying to find a document that describes adding a delay between the inverted lock signal of one DCM that...
3 comments posted 19yrs
posted by bradsmallridge
3 comments posted 19yrs posted by bradsmallridge

XCF02S + Spartan 2e JTAG config problems

I'm seeing some strange behavior when trying to program a Spartan 2e (XC2S150E) directly via JTAG. In the system it is...
3 comments posted 19yrs
posted by gabor
3 comments posted 19yrs posted by gabor