I am new in this field and I have been working with ISE Xilinx tool. When I want to create a testbench waveform I have to insert several values, two of them are: Input setup time & Output valid delay. I do not understand them:
Thank you!.
Jajo
Jajo,
They are related to external connections. The setup time is asking "How long before your clock source is the data guaranteed to be valid". The output valid delay time is asking "How long after your input signals does it take for your output to be valid". The testbench waveform can use a complete system timing model to generate a valid simulation for post-routed designs.
Assuming you are just getting started ... set them to 0 (ideal) for now. It will allow you to get your logic correct. Then once your device targeting is done you can deal with the timing issues. (Since you don't know what they are you are probably not even really targeting a device yet).
Trevor
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