Hi to everyone, I'm developing some electronics to make a time measurement with a resolution of 25 ps. I'm using a dedicated ASIC to do so but I'm giving the signals to the ASIC through an FPGA. The way is very simple, basically I have some signals coming to my fpga which I will mask with some combinatorial logic and a configurable register so that I can allow some measurements or some others. The output of this "masking" will go to the ASIC. They assert (and here is the question) that a clocked device as an FPGA may add some jitter to the signals due to the substrate current overload (for the presence of the clock) that will lead to some 15 ps jitter over the signals. I don't know how they could resolve this value but I'm assuming they were telling the truth about numbers (at least, while I have some doubts about explanation of those numbers). Can anyone say something about this? Does it sound reasonable?
Al