Hi everybody,
A part of a project I'm designing is a PCMCIA bus card with a 32 bit data system bus. The system included in the card has a multicore DSP, an ARM processor, some NOR FLASH, SDRAM memory and a FPGA. The FPGA is used for the PCMCIA interface to the system bus and some high speed math as a companion for DSP. The purpose of the whole PCMCIA interface is to transfer some data from the SDRAM into PC, in real time at 33Mhz clock rate. The card data system bus is running at 133MHz.
How you'll chose the design for the best card bus interface, knowing there are some fast processes on the internal bus:
a. using the FPGA as a slave memory selected by the DSP and implementing a FIFO inside the FPGA . An interrupt request will notice the PC to start download data and empty the FIFO. b. using DMA control over the system bus from the FPGA (FPGA as master, DSP as slave) c. other (please detail)
thank you, Vasile