I have declared a state in VHDL like this:
type state_type is ( state1, state2, state3, state4, state5, state6, state7, state8); signal state: state_type := idle;
and used it like this:
test_process: process(clock, reset) begin if rising_edge(clock) then case state is when state1 =>
inverter_test
Hello Frank,
The problem you have referred to namely power up initialization and its interaction with state machine encloding has been fixed in Quartus II 6.0 SP1 which can be downloaded form teh Altera web site.
H> I have declared a state in VHDL like this:
snipped-for-privacy@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de
Thanks, I'll try it next week. I have encountered the problem in Quartus II
6 without service pack, so maybe SP1 will solve it and I can undo the manual encoding of the states.-- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
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