Field-Programmable Gate Arrays

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FFT on Virtex II Pro (how to download .dat file?)

Hello, I am using FFT v.3.2 core from Xilinx to implement FFT algorithm on FPGA. I would like to download .dat file as...
0 comments posted 19yrs
posted by m.vitaliy
0 comments posted 19yrs posted by m.vitaliy

Query :Regarding Synthesis Report

At the fourth line of the report, there is mention about CPU time and Elapsed time. Similarly at the end of the report,...
2 comments posted 19yrs
posted by karthik.anantha
2 comments posted 19yrs posted by karthik.anantha

Implementing DVI EDID on Stratix II GX?

Hello, I have a project which will require a DVI output and was wondering if it is possible to have the FPGA do the DVI...
1 comments posted 19yrs
posted by jjlindula
1 comments posted 19yrs posted by jjlindula

Looking for simple Cycone 2 example design

I'm looking for a complete project containing a minimal VHDL design for the Cyclone II, preferably 2C35 or similar to h...
1 comments posted 19yrs
posted by mike
1 comments posted 19yrs posted by mike

Organization of character bit maps

Hi, I want to design a character generator. Using Lattice XP EBR blocks I have the following architecture of the RAM bl...
1 comments posted 19yrs
posted by ALuPin
1 comments posted 19yrs posted by ALuPin

source synchronous timing (Xilinx)

Hello, I am trying to constrain a source synchronous input to a Spartan 3E FPGA. On the website: http://toolbox.xilinx....
1 comments posted 19yrs
posted by Karel.Deprez
1 comments posted 19yrs posted by Karel.Deprez

About Unstable Operation of ACTEL(A3P1000)....

Hi.. I can't understand about this situation.... I use same source(VHDL), same program tool(Libero), same device(A3P100...
7 comments posted 19yrs
posted by kypilop
7 comments posted 19yrs posted by kypilop

FPGA : LIFO

Hi I wanted some help or pointers in Asynchronous LIFO design. My read and write clocks are asynchronous, I don't know...
2 comments posted 19yrs
posted by pbijoy
2 comments posted 19yrs posted by pbijoy

About partial reconfiguration in Virtex 4

Hi all, It seems that run-time reconfigurations are only available in DCM and RocketIO blocks. Concerning about partial...
2 comments posted 19yrs
posted by lipeng.net
2 comments posted 19yrs posted by lipeng.net

Recursive component instantiation

Does synplify support recursive component instantiation, i.e. a component which instantiate its own entity within its ar...
7 comments posted 19yrs
posted by no-replay
7 comments posted 19yrs posted by no-replay

testbench help

get the following error while trying to create a test bench. ERROR:Portability:90 - Command line error: Unexpected argu...
1 comments posted 19yrs
posted by
1 comments posted 19yrs posted by

FPGA+Ethernet

Hi all, I want to add an Ethernet interface to my FPGA board for data transmission. But I'm not sure which scheme I sho...
7 comments posted 19yrs
posted by eejju
7 comments posted 19yrs posted by eejju