Field-Programmable Gate Arrays

Query :Regarding Synthesis Report

At the fourth line of the report, there is mention about CPU time and Elapsed time. Similarly at the end of the report,...

2 comments posted 19yrs

posted by karthik.anantha

2 comments posted 19yrs posted by karthik.anantha

Implementing DVI EDID on Stratix II GX?

Hello, I have a project which will require a DVI output and was wondering if it is possible to have the FPGA do the DVI...

1 comments posted 19yrs

posted by jjlindula

1 comments posted 19yrs posted by jjlindula

Looking for simple Cycone 2 example design

I'm looking for a complete project containing a minimal VHDL design for the Cyclone II, preferably 2C35 or similar to h...

1 comments posted 19yrs

posted by mike

1 comments posted 19yrs posted by mike

Organization of character bit maps

Hi, I want to design a character generator. Using Lattice XP EBR blocks I have the following architecture of the RAM bl...

1 comments posted 19yrs

posted by ALuPin

1 comments posted 19yrs posted by ALuPin

source synchronous timing (Xilinx)

Hello, I am trying to constrain a source synchronous input to a Spartan 3E FPGA. On the website: http://toolbox.xilinx....

1 comments posted 19yrs

posted by Karel.Deprez

1 comments posted 19yrs posted by Karel.Deprez

About Unstable Operation of ACTEL(A3P1000)....

Hi.. I can't understand about this situation.... I use same source(VHDL), same program tool(Libero), same device(A3P100...

7 comments posted 19yrs

posted by kypilop

7 comments posted 19yrs posted by kypilop

Problem with connecting higher order address lines of SDRAM to FPGA

Hi I have done a SDRAM controller design in spartan. using Micron SDRAM(128Mx32 with 4 banks). If I access SDRAM using...

7 comments posted 19yrs

posted by amirtham

7 comments posted 19yrs posted by amirtham

FPGA : LIFO

Hi I wanted some help or pointers in Asynchronous LIFO design. My read and write clocks are asynchronous, I don't know...

2 comments posted 19yrs

posted by pbijoy

2 comments posted 19yrs posted by pbijoy

query regarding capacitance of pins of cyclone device

Dear friends I found out input capacitance for pins of cyclone IIEP@C20Q240C8devices 1)CIO Input capacitance for user I...

0 comments posted 19yrs

posted by vsrpkumar

0 comments posted 19yrs posted by vsrpkumar

About partial reconfiguration in Virtex 4

Hi all, It seems that run-time reconfigurations are only available in DCM and RocketIO blocks. Concerning about partial...

2 comments posted 19yrs

posted by lipeng.net

2 comments posted 19yrs posted by lipeng.net

Recursive component instantiation

Does synplify support recursive component instantiation, i.e. a component which instantiate its own entity within its ar...

7 comments posted 19yrs

posted by no-replay

7 comments posted 19yrs posted by no-replay

testbench help

get the following error while trying to create a test bench. ERROR:Portability:90 - Command line error: Unexpected argu...

1 comments posted 19yrs

posted by

1 comments posted 19yrs posted by

RTL Hardware design issue: Count Leading Zeros CLZ

Hi, I'm trying to create a Count Leading Zero (CLZ) in VHDL for a project but i'm having difficulty in finding any info...

9 comments posted 19yrs

posted by davidc

9 comments posted 19yrs posted by davidc

FPGA+Ethernet

Hi all, I want to add an Ethernet interface to my FPGA board for data transmission. But I'm not sure which scheme I sho...

7 comments posted 19yrs

posted by eejju

7 comments posted 19yrs posted by eejju

differential I/O with ISE 8.2 / spartan3E

I am new to fpga design... and don't know the good practice to handle differential I/O. I am right using OBUFDS and IBU...

2 comments posted 19yrs

posted by rponsard

2 comments posted 19yrs posted by rponsard