Hi.. I can't understand about this situation.... I use same source(VHDL), same program tool(Libero), same device(A3P1000) and same programmer(FlashPro3)....But the device operation is not regular.... I test some functions using StartKit from Actel Co. Many times, parts of function are un-operation.... The un-operated functions are not fixed !!! Malfunctions are irregular..................... Also, the source of VHDL had been verified in Altera device (EPF10K100ARC240) In Altera, all functions are operated correctly........... Always, Actel's programmer said "Verifying Passed"....Is that true???? Plz, help me.... I lost self control using Actel's device.... Help me, Help me
You are not giving enough information about your board, about your design, about the tool versions, about the VHDL, about the timing constraints etc etc etc.
If you want people to help you then you really need to learn how to ask meaningful questions.
The board is A3PE-A3P-EVAL-BRD1 REV3 which is manufactured by Actel Co. This board has expantion port for I/O, some LEDs, 1 LCD and regulators, just simple design.
Libero version is 7.2 FlashPro Program version is 4.2 Synflify version is 8.1 for Actel
The tested VHDL source has function of serial communication(UART). And always, LED blink correctly in VHDL source But serial communication function operates unregular Sometimes Reciever operates well, But Transmitter is not. Sometimes Transmitter operates well, But Reciever is not. X-tal is 11.0592MHz and operates correctly. Supply voltage is 3.3V for I/O which supplied by Application board from Actel As I know, TTL level can adapt CMOS 3.3V Power ground was one point. And I use RS232 to USB converter, but they operate well. Self test passed.
I don't know well about timing constraints which is default option. But palce&router of Actel said satisfying the timing constraint.
Are U want any informations? Plz, let me know.. I'm beginner of FPGA.. :-) Are there some options or parameters to consider for palce&route ? Thx to Alan Myler for your advice :-)
first of all, if you want to ask questions, please respect the newsgroup "netiquette". there are already way too many "plz help!!! design doesnt work!!!" posts on this NG.
that being said, lets take a look at your problem. i am not an expert, hopefully i can do some helping anyway :)
A very simple board, rock solid FPGA. Ive never had any problems with that one. but as far as i know, they come with a A3P250, not a A3P-1000...
but there are no UART connectors on this board?
Either your board or FPGA is borken, or its your VHDL design. I would bet on the latter.
the default board clock is 40. are you using a PLL? some of the PLLs are not powered on some actel boards, and sometimes Designer chooses to use one of them. check your boards documentation!
that doesnt prove anything. find a scope and check the TX signal manually. and I wouldnt add extra sources of failure when things arent working, connect the UART directly to your PC!
do you actually _have_ any? in any case, i dont think something as simple as an UART could have timing problems.
I usually get this kind of behavior when i forget to synchronize external signals before reading them. google for "Peter Alfke" and "Metastability" for more info.
I dont think it has anything to do with the FPGA vendor. I have had the same quick'n-dirty UART design running on actel, xilinx, altera and lattice boards without any problems.
your problem could of course have something to do with the different clocks on each board, maybe in some cases the _derived_ uart clock differs a few percent too much against the ideal UART clock??
that means that flash pro writes your program to FPGA, then reads it back to make sure there were to communication errors. note that some actel FPGAs cant do readback, so the flash pro tool sometimes says Verifying Passed" without really checking.
no, the default options are usually ok.
one last thing, the Libero tool comes with a _superb_ beginner tutorial (there are also videos on their web site), which explains everything from creating a project to post-layout simulation. have a good look at those document, then do a post-synthesis simulation to find those nasty bugs.
Do you use the same synthesis software for the Altera device? For some "broken" [1] code, you will see different tools generating functional different output
There are several reasons why your design won't work in a actual device even if you allready had your design successful running on another device. Even valid code and usage of the the same tool may result in different functionality, if you had timing problems or forget to set needed timing constraints.
bye Thomas
[1] Some code has to be considered broken, if it is legal vhdl, but wrong supported, more often you have nonstandard code which is accepted by some tools, but may result in different functionality on different tools.
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