Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

PlanAhead : problems

Hi, After using PlanAhead a while I've got some problems: 1) when using ExploreAhead Trace does not start. I investigat...
0 comments posted 19yrs
posted by wojtek2u
0 comments posted 19yrs posted by wojtek2u

Microblaze LMB bus

Hi Does microblaze do all the LMB transfers synchronously (ie, it doesnt support variable latency). If so, why is there...
6 comments posted 19yrs
posted by vmurali
6 comments posted 19yrs posted by vmurali

Xilinx PAR crashing with 'make'

I'm trying to get the PAR tool to run using makefiles and it consistently crashes with the message: Starting Placer Pha...
4 comments posted 19yrs
posted by johnp3+nospam
4 comments posted 19yrs posted by johnp3+nospam

Registers initial values with Altera Stratix II

Hi, I've been using X FPGA for years and I often use the following VHDL initial value assignment, especially for finite...
1 comments posted 19yrs
posted by fchoquette
1 comments posted 19yrs posted by fchoquette

ANNC: SERDES Fundamentals Webcast

Lattice is holding a webcast tomorrow Thursday, December 7, "SERDES Fundamentals." The presenter will be Bertrand Leigh...
0 comments posted 19yrs
posted by bart.borosky
0 comments posted 19yrs posted by bart.borosky

FPGA to Camera (Channel) link

Hi I want to connect an LVDS output from a Stratix II FPGA to a Camera Link frame grabber, but I can't figure out how I...
3 comments posted 19yrs
posted by avishorp
3 comments posted 19yrs posted by avishorp

XSA3S1000 board and SDRAM

Hello, My application needs to write the on booard SRAM with the data and then read the data from the FPGA. I saw the a...
0 comments posted 19yrs
posted by conphiloso
0 comments posted 19yrs posted by conphiloso

VHDL Variable Length Input file.

I have a test bench in which the input stimulus file length is unknown. I would like to read the file in to my test ben...
2 comments posted 19yrs
posted by ted.franklin3
2 comments posted 19yrs posted by ted.franklin3

How to reduce jitter of 30-bit accumulator

Hello, I have a 30-bit accumulator in which I use the last bit as my clock out to the design. In the following way: alwa...
3 comments posted 19yrs
posted by amir.motiuk
3 comments posted 19yrs posted by amir.motiuk

Remove DCM wrappers from EDK designs

Hi, I'm working on a partial reconfiguration design and need to validate an assumption. This question isn't directly re...
1 comments posted 19yrs
posted by dpmontminy
1 comments posted 19yrs posted by dpmontminy

How to find an FPGA board

How do I make sense out of the list of boards in the FAQ, other then going through them one at a time. It would help if...
4 comments posted 19yrs
posted by wburris
4 comments posted 19yrs posted by wburris

How do I delay signal to pad?

I have Xilinx FPGA and need to delay a signal to pad. It is not a clock. I would like to do this in the constraints file...
1 comments posted 19yrs
posted by seabass950
1 comments posted 19yrs posted by seabass950

help with Xilinx LVDS syntax

I apologize if this questions has been answered already. I was unable to find an answer in my search through this group...
0 comments posted 19yrs
posted by morgank
0 comments posted 19yrs posted by morgank