source synchronous timing (Xilinx)

Hello,

I am trying to constrain a source synchronous input to a Spartan 3E FPGA. On the website:

The thing that I don't understand is the constraint for the falling edge:

TIMEGRP DATA_IN OFFSET IN = 4 VALID 3 BEFORE CLK TIMEGRP FF_FALLING;

Why do they use 4 ns in this example? I can't relate it to the timing diagram that is shown.

thanks and best regards, Karel