Latest threads in Field-Programmable Gate Arrays

Xilinx doesn't detect setup/hold violations on synchronous reset

Hi all, I am facing some problems with Xilinx ISE 8.2 not taking into account synchronous reset setup/hold violations o...

6 19yrs

maybetooparanoid

6 19yrs maybetooparanoid

Atmel release Metal Programmable Cell Fabric uC ARM9

http://www.atmel.com/dyn/corporate/view_detail.asp?FileName=CAP9_5_21.html Atmel have done mask-metal flows for many ye...

4 19yrs

no.spam

4 19yrs no.spam

How to copy hex data from Quartus vwf file to text?

I'm just getting started with Quartus II v7.0. I have a test vwf file for some existing vhdl. I'd like to copy the 128...

0 19yrs

harold

0 19yrs harold

ModelSim version upgrade problem from 6.1c to 6.2c

Hi, When my ModelSim version is upgraded from 6.1c to 6.2c, a new problem happens: When opening wave.do file, either cr...

1 19yrs

wtxwtx

1 19yrs wtxwtx

Does FPGA need CPU for processing a packet/frame

I would like to know if an FPGA needs CPU for processing a packet/ frame that it receives. For example an FPGA is capab...

11 19yrs

hetzme

11 19yrs hetzme

SelectIO banking rules

Hi, Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same bank even if there is VCCIO problems ? Thanks!

7 19yrs

lpaulo07

7 19yrs lpaulo07

Error in NGDBuild

Hello everybody, I was trying NGDbuild for a DDR memory controller implementation. I am getting the following error: ER...

1 19yrs

koustav79

1 19yrs koustav79

Cyclone FPGAs in Switzerland

EHLO (o; I tried several weeks ago to contact EBV Switzerland where to get EP1C and EP2C devices in smaller quantities...

3 19yrs

me

3 19yrs me

Timing not met but working on board

Hi all, I developed a design in which i need a master clock of 90Mhz, so during synthesis max. freq obtained is 56Mhz a...

9 19yrs

jrgodara

9 19yrs jrgodara

Filtering the FPGA reset signal

Hello, On my board, the FPGA receives its reset_n signal from a voltage supervisor IC (such as MAX635x or LM370x). Is t...

3 19yrs

eliben

3 19yrs eliben

UART Receiver Parity Check

Hello, I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming par...

2 19yrs

Anson.Stuggart

2 19yrs Anson.Stuggart

AccelDSP Systemgenerator ML403

Hello, i need help with my ml403. I would like to get a my ML403 Board from Xilinx run with Systemgeneratior. That i ca...

0 19yrs

erixx

0 19yrs erixx

Signal Assignment bugs in Quartus-II ... AGAIN!

I've repeatedly reported this blatant and repeatedly acknowledged bug in Quartus-II's schematic editor, yet it appears...

5 19yrs

edick

5 19yrs edick

external clock frequency doubles

Hi People, I am attempting to interface the Xilinx Virtex - II Pro FPGA with a quad channel codec. I am using XC2VP30-F...

3 19yrs

get2venu

3 19yrs get2venu

EDK 8.1i to EDK 9.1i UCF file errors

Hello, In our *working* EDK 8.1i project, we locked a DCM in the following manner in the UCF file (located in /data/sys...

3 19yrs

njoroge

3 19yrs njoroge

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