Field-Programmable Gate Arrays

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Does FPGA need CPU for processing a packet/frame

I would like to know if an FPGA needs CPU for processing a packet/ frame that it receives. For example an FPGA is capab...
11 comments posted 19yrs
posted by hetzme
11 comments posted 19yrs posted by hetzme

SelectIO banking rules

Hi, Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same bank even if there is VCCIO problems ? Thanks!
7 comments posted 19yrs
posted by lpaulo07
7 comments posted 19yrs posted by lpaulo07

Error in NGDBuild

Hello everybody, I was trying NGDbuild for a DDR memory controller implementation. I am getting the following error: ER...
1 comments posted 19yrs
posted by koustav79
1 comments posted 19yrs posted by koustav79

Cyclone FPGAs in Switzerland

EHLO (o; I tried several weeks ago to contact EBV Switzerland where to get EP1C and EP2C devices in smaller quantities...
3 comments posted 19yrs
posted by me
3 comments posted 19yrs posted by me

Timing not met but working on board

Hi all, I developed a design in which i need a master clock of 90Mhz, so during synthesis max. freq obtained is 56Mhz a...
9 comments posted 19yrs
posted by jrgodara
9 comments posted 19yrs posted by jrgodara

Filtering the FPGA reset signal

Hello, On my board, the FPGA receives its reset_n signal from a voltage supervisor IC (such as MAX635x or LM370x). Is t...
3 comments posted 19yrs
posted by eliben
3 comments posted 19yrs posted by eliben

UART Receiver Parity Check

Hello, I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming par...
2 comments posted 19yrs
posted by Anson.Stuggart
2 comments posted 19yrs posted by Anson.Stuggart

AccelDSP Systemgenerator ML403

Hello, i need help with my ml403. I would like to get a my ML403 Board from Xilinx run with Systemgeneratior. That i ca...
0 comments posted 19yrs
posted by erixx
0 comments posted 19yrs posted by erixx

Signal Assignment bugs in Quartus-II ... AGAIN!

I've repeatedly reported this blatant and repeatedly acknowledged bug in Quartus-II's schematic editor, yet it appears...
5 comments posted 19yrs
posted by edick
5 comments posted 19yrs posted by edick

external clock frequency doubles

Hi People, I am attempting to interface the Xilinx Virtex - II Pro FPGA with a quad channel codec. I am using XC2VP30-F...
3 comments posted 19yrs
posted by get2venu
3 comments posted 19yrs posted by get2venu

EDK 8.1i to EDK 9.1i UCF file errors

Hello, In our *working* EDK 8.1i project, we locked a DCM in the following manner in the UCF file (located in /data/sys...
3 comments posted 19yrs
posted by njoroge
3 comments posted 19yrs posted by njoroge

How do I constraint multiple clock cycle in Altera?

Hello everybody, My Altera design uses multiple clock cycle and negative clock edge, how do I constraint it? Here is my...
1 comments posted 19yrs
posted by newsreader
1 comments posted 19yrs posted by newsreader

How to insert tab in Write() function in VHDL

Hi, I want to insert tab in write() function in VHDL. Here is a write() function definition: procedure WRITE(L : inout...
9 comments posted 19yrs
posted by wtxwtx
9 comments posted 19yrs posted by wtxwtx