Field-Programmable Gate Arrays

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FPGA vs ASIC

When it comes to designing for fpgas or asics there are a lot of guidelines/rules that need to be followed consistently...
32 comments posted 19yrs
posted by fpgabuilder-groups
32 comments posted 19yrs posted by fpgabuilder-groups

"SPI indirect" programming for any FPGA/CPLD

Hi attached to xilinx forum message http://forums.xilinx.com/xlnx/board/message?board.id=OTHERIP&thread.id=19 is a simp...
0 comments posted 19yrs
posted by Antti.Lukats
0 comments posted 19yrs posted by Antti.Lukats

Power supply filter capacitors

I'm woefully undereducated to be doing this, but I figure the best way to learn is by doing, so I need a little help wi...
33 comments posted 19yrs
posted by nevo_n
33 comments posted 19yrs posted by nevo_n

Question about the clocks power in XPower.

Hello, All, T the clocks power results given by the XPower are always 0 when I tested my designs. But there must be som...
0 comments posted 19yrs
posted by pang.dudu.pang
0 comments posted 19yrs posted by pang.dudu.pang

fgpa beginner

I'm a beginner with FPGA and I want to dive into the digital video filtering, analysis and display. I can clearly imagi...
4 comments posted 19yrs
posted by tirsys
4 comments posted 19yrs posted by tirsys

ISE PACE Question

HI, I have a Xilinx ISE - PACE editor question- I am using the schematic editor for now just to get familar with the to...
1 comments posted 19yrs
posted by rg.jones
1 comments posted 19yrs posted by rg.jones

Signetics N82F101F

Hello all Does anyone have a Signetics data sheet / data book with this part? Thank you
5 comments posted 19yrs
posted by tagough
5 comments posted 19yrs posted by tagough

is Quartus 7.1 really that S*** !?

Hi so far I hear that "Altera tools are getting better" - now I wonder how long should one wait til they become useable...
9 comments posted 19yrs
posted by Antti.Lukats
9 comments posted 19yrs posted by Antti.Lukats

xilinx spi flash programming

I'm about to place an SPI flash for spartan 3e but I'm a bit disapointed in having to place another header to program i...
7 comments posted 19yrs
posted by colin_toogood
7 comments posted 19yrs posted by colin_toogood

builing a SPI interface in vhdl

HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let an fpga read and write a flash memory. The fpga i...
7 comments posted 19yrs
posted by giuliopulina
7 comments posted 19yrs posted by giuliopulina

MPMC2 NPI Help!

I am using the MPMC2 to implement a PLB and NPI port config. The PLB port works as expected. However, I am simulating m...
9 comments posted 19yrs
posted by mottoblatto
9 comments posted 19yrs posted by mottoblatto

Paper about selecting fixed point bit widths?

Hello all, Can anyone point me to a good general purpose paper about selecting appropriate bit-widths for a fixed point...
3 comments posted 19yrs
posted by paragon.john
3 comments posted 19yrs posted by paragon.john

MGT

Hi all, I am trying to use a Aurora Core and MGT transceiver to get high Speed serial transmission signal out. I have r...
5 comments posted 19yrs
posted by shakith.fernando
5 comments posted 19yrs posted by shakith.fernando

Multilinx and chipscope

Hi all, I've got a question about Multiplinx ( USB/JTAG interface) and ChipScope Pro. I'm using ISE 9.1i and I would li...
0 comments posted 19yrs
posted by michel.talon
0 comments posted 19yrs posted by michel.talon