Power supply filter capacitors

I'm woefully undereducated to be doing this, but I figure the best way to learn is by doing, so I need a little help with my current project.

I'm designing a lighting dimmer around the Altera Cyclone EP1C6 in the 240 pin package. I will be using the chip to turn on and off up to 128 optoisolators at a frequency of 120Hz. (The optos will feed the gate pins of TRIACs which will turn Christmas lights on and off. By turning the optos on in the middle of an AC half-cycle I plan on getting dimming in addition to on/off.)

Each opto will draw a maximum of 7mA. The FPGA will be sinking the current from the opto, not sourcing current.

Absolute worst case would be all 128 channels switching simultaneously, although I doubt that would happen very frequently. (For one, I don't have enough circuits to drive 128 strings of Christmas lights without tripping a breaker at the house.)

I have no clue how to determine what size capacitors to put between the VCCIO pins and GND. If anyone could give some guidance, I'd appreciate it. (If you happened to use my particular implementation as an example, I'd appreciate it that much more!)

Thanks, all!

-Matt

Reply to
Nevo
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Not really answering your question, but... Sink or source, 128 x 7mA is a lot, your FPGA may not be able to handle it. You probably need something a bit more efficient or maybe an extra level of transistors to give current gain.

Reply to
Chris Maryan

Yes, this is on my list of concerns. For the time being I plan on solving the problem by using the "don't do that!" method. I started *way* too late to be ready for a Christmas light show so I won't be able to really fix this problem this year.

Reply to
Nevo

You can never have too much capacitance on the VCCIO, in my opinion. At 120 Hz, it should be easy for you to stagger the output timing of the various triac drivers without materially affecting the dimming quality. This would reduce the issues of simultaneous switching and also reduce the high-speed decoupling requirements on VCCIO.

However there may be another issue that gets you in the end. Where are you mounting all the triacs and how easy is it for the triac switching noise to find its way back to the FPGA power system? Even with optocouplers, if your input supply shares AC wiring with the triac AC system you may be in for trouble. Think about any possible coupling paths.

Have Fun, Gabor

Reply to
Gabor

I don't understand how he can do this. For a given brightness, doesn't this fix when he has to switch on the triac?

(There's no choice about when to switch off: it won't switch off until the current falls to zero at the end of the half-cycle).

Mike

Reply to
MikeShepherd564

If you stagger in nanoseconds it won't have a large effect on the light output, which may be in the 100 microsecond range. (A half cycle is 8.333ms, one hundredth is 83.33 microseconds.) Even so, you can stagger them between cycles and average to the desired value. That would be more true for large light bulbs (such as use in theaters) than for small christmas lights.

-- glen

Reply to
glen herrmannsfeldt

Staggering sub-millisecond sounds like a good idea (up to the point where the largest brightness error is unacceptable).

Averaging over several half-cycles would need some experiment. Perhaps it could work for very high-power bulbs (those with a lot of thermal inertia), but for domestic bulbs (say 100W), the flicker would soon become visible (well before it reaches the level where the same error in "constant" brightness would cause a problem).

Mike

Reply to
MikeShepherd564

Nevo; Perhaps you could play (uh,experiment) with with a microprocessor development board (PIC, AVR, etc) to get ideas on what works and doesn't work to control your Christmas lights. You could probably get something working sooner than designing an FPGA project from scratch.

-Dave Pollum

Reply to
Dave Pollum

I was just yesterday wondering how much current newer FPGAs can sink. I was figuring if I could direct drive a floppy disk interface without TTL buffers. I didn't look it up yet, though.

-- glen

Reply to
glen herrmannsfeldt

We're drifting a little from the topic, but...

To avoid visible flicker at any brightness, the jitter between the supply waveform and the triac switching point must be no more than a few microseconds. (Remember that the supply is asynchronous to the processor clock, so you must detect its "crossing zero" on every half cycle and start some kind of timer - hardware or software - at that point, then drive the triac for a short time when the timer expires).

Without hardware support (and even driving only one triac), you need very tight microcontroller code to achieve only this. The rest of the code (with which you're trying to experiment) would be severely distorted by the needs of this triac driver.

For this reason, it's probably best to develop the triac timing logic in "hardware" (probably an FPGA) right from the start, so the micro can be devoted to the high-level control, for which it will then have plenty of time to control several channels via the FPGA

Mike

Reply to
MikeShepherd564

Gabor,

Thanks for the input.

I hadn't thought of staggering the switching times. That's a great idea. The software that I'm using to drive the lights won't do that, but I probably have enough logic elements left in the FPGA to implement that in hardware.

I wonder... how can I get a feel for how much delay would reduce the need for high capacitance on VCCIO? (I'm a biologist by training, mad scientist by night.)

As for the line noise getting back to the FPGA... well, this is for a residence and it's 100% likely the FPGA circuit will be on the same power leg as some of the TRIACs, and highly likely to be on the same circuit, even. In my case, they will be mounted a large physical distance from the FPGA and have long extension cords, but I know there's no snubber circuit on the TRIACs. I suppose extra capacitance and inductance on the FPGA's power supply could help combat that?

Reply to
Nevo

Bah... the homebuilt community has already done that! What's the fun in that? :)

Seriously, I've decided to go with an FPGA for a few reasons:

1) The number of I/O pins on a uC is limited compared to FPGA 2) The processing power of a uC limits the number of channels that can be dimmed 3) The per-channel cost is going to be much lower with an FPGA than a uC 4) I've done the uC thing. FPGA's are a new frontier for me to explore!

I've prototyped my FPGA design driving LED's and have verified the basic design of the logic. Repeating it 128 times is trivial in an FPGA (not so much in a microcontroller). The only new twist in scaling up from my tests is the addition of a zero crossing detector.

The fourth reason above is my main motivation for doing this: I get to learn something new! Even if it doesn't work by Christmas I'll get the education out of it.

Reply to
Nevo

Everyone,

I really appreciate the input I've received on this thread. Y'all have been great and have given me a lot to think about. Reading this thread has been a lot of fun and has been very educational.

However, I'm not sure that I've adequately desribed the depths of my ignorance on this subject. I literally have no idea what size capacitors to use... not even a guess as to the order of magnitude. A few picofarads? A few hundred microfarads? Really... I'm that clueless.

If someone could just throw out a number that makes some kind of sense, I'd appreciate it.

(I promise I will never go professional in your industry without the obtaining the requisite formal education first!)

Reply to
Nevo

If you're working from an on-board LDO linear regulator (Low Drop Out), the regulators often have a stable range of output capacitance and a recommended input capacitance. If you plan on supplying a wall-wart power supply to drive your device, things might get a little ugly in the tolerance of the system over the long wires even with a large bulk capacitor.

I'd recommend figuring out what current you need at what voltage(s), design in an appropriate LDO, follow their input/output capacitor suggestions, and stagger the turn-on of your individual channels.

By keeping the current *changes* small, the capacitance needed is on the order of a microfarad or less rather than tens or hundreds of microfarads. If you have your LDO designed with an appropriate output capacitance, a dozen 0.1 uF surface-mount caps around the part should be wholly sufficient. The "bulk" capacitance at the LDO - along with the regulator itself - takes care of all the low-frequency current needs and the dozen 0.1 uF caps takes care of any current steps. Take a look at the selected regulator's transient response and you get an appreciation for the number of channels you can turn on at once and have the low-frequency voltage needs met. The desire to stagger the outputs comes down to 1) making sure you don't switch 100% of your optos in a couple microseconds for the LDO's sake and 2) keeping the simultaneous "per-clock" changes small to avoid "ground bounce" problems; this takes care of most of the I/O challenges alone. To help with the nano-second scale I/O switching current surge and to accommodate the rest of the minor on-chip functionality, you need those small, physically distributed caps.

Also, since your turn-on and turn-off times don't need to be sub-nanosecond, be sure to specify slow output drive for your I/Os. Specifying 8mA drive in combination with current limiting resistors to your optocouplers will keep each current step from sucking down too much instantaneous current before settling down. Even though it's specified as "8 mA" the outputs will drive much more than that when they're trying to transition and will give you the full current at the specified output voltage level.

Your modern FPGA probably has different rails for the I/O and for the core. If your I/Os are all that are driven by the one regulator, the high frequency decoupling could be sloppy and your system wouldn't notice as long as the LDO is happy with its output capacitance. The core voltage is where the transient suppression is more important. If you're working at "slow" speeds of 20 MHz and below, those transients are relaxed compared to much of the modern designs out there and the "dozen 0.1 uF caps" I recommended before is probably more than you need. Increasing the capacitance value is probably not as helpful as having the 12 devices. Even changing the 12 devices to 0.01 uF caps might be fine but they cost the same, so stick with the ubiquitous 0.1 uF chips.

Capacitance is only a small part of the overall power scheme. Are you designing a 4-layer board? What device and package are you planning on using? Our days of wire-wrap prototyping are long behind us. If you have a quick PCBoard prototyping service you plan to use that can give you 4-layer boards, the solid ground planes and solid sections of power planes on the inside layers should give you good results with the small scattering of caps. The "dozen caps" would be overkill if you're using a 36-macrocell CPLD but an FPGA with 128 I/O might want the full complement. The dozen value works out reasonably from a layout and convenience standpoint, not because those values are what you absolutely need.

Let us know how your project goes.

- John_H

Reply to
John_H

Hi Nevo, One 0402 1uF cap per Vcco pin. Make sure your circuit board has a ground plane. You can't* go wrong! HTH., Syms.

  • Probably!
Reply to
Symon

A mixture of capacitor values; even if your design is not clocked very fast, the I/O pins are capable of high speed transitions, so you can't ignore the HF (low value) capacitors altogether, though IMO you'll need a few hundred uF somewhere on the PCB too.

Here's the party line from Xilinx...

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...which may be more than you need for a hobby project, but what price is a capacitor?

I WOULD try to use a ground plane if you can; For this application I wouldn't worry about the "signal integrity" and trace impedance and simulating long traces AT ALL except for the clock signals and configuration signals (where I'd just keep them short)...

- Brian

Reply to
Brian Drummond

John,

Thanks so much for your input. You clearly spent quite a bit of time helping me out, so let me answer as best I can. (I decided to include your post in my reply for reference.)

I am indeed working from an onboard LDO regulator. After reading your reply I figured I need, worst case, to drive 160 circuits at 3.3V at 7mA. Hopefully the board will never be called upon to actually do that, but that's the worst case. That's 1.12 amps from the regulator. (0.896 of that would be driven through the FPGA, which we've already established in this thread is a questionable practice at best.) In addition, the 3.3V rail will feed a 1.5V LDO to supply power to the FPGA's logic core.

After searching digikey's website for a LDO that could deliver that current at low price, I settled on the LD1085V33 from ST Micro. I've looked through the datasheet and don't see any explicit mention of capacitor values for the input and output, but the sample application circuit shows 10uF on the input and 10uF on the output.

So... does this mean the total capacitance of my board (btwn 3V3 and GND), including bypass caps on the chips, should roughly equal 10uF?

Figures 22 and 23 in the datasheet show the response of the regulator to load transients, but I'm honestly not quite sure how to interpret the data.

I've designed a 4-layer board, with a 3V3 plane and a GND plane. I'm running the 1V5 net to power the core logic on 50mil traces on an outer layer of the board. (Is there any big advantage to putting them on an internal layer?) The FPGA is an Altera Cyclone in the 240QFP package.

The highest switching frequency for the core logic will be 4MHz. A 4MHz oscillator drives a 32 bit counter that is reset on each zero crossing. The resulting number is hardware divided by 256 to get 'number of clock cycles per dimming level'. A host computer will send data to drive the channels. The FPGA is essentially a very long serial shift register. The computer clocks in 128 channels * 8 bits/channel of data over a DATA and a CLK line, then loads the data into latches with a STROBE line. (Basically, a really long 74HC595 chip.) I haven't measured the data rate, but I estimate the incoming data is ~1MHz. I'll put a LVDS driver at the host computer and send the signals down CAT5 cable to my board where the FPGA will get it on LVDS input pins. Additional logic compares the output from the channel's 8-bit latch agaist the current 'dimming level' from the counter driven by the 4MHz oscillator, and turns on the output when they match.

So... I'll conclude that a 10uF bulk capacitor at the regulator, a 0.1uF cap at each VCCIO pin (total of 12), slow output drive on the FPGA pins, low current drive on the FPGA pins, staggering the turn on time, and a little positive attitude should get me where I want to go.

Thanks so much, everyone, for your suggestions on this thread. Let me just say that I'm glad I'm not in some of your shoes, designing multi-hundred-megahertz speed designs!

Reply to
Nevo

Why not using an additional driver transistor? Like at page 7 in this datasheet described:

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Could be a small SMD transistor, which costs only cents and limits your control current to 0.5mA without problems (but I think in figure 11 of the datasheet a resistor in the base of the transistor would be good) or even a small signal FET, which draws nearly no current. Maybe you should use an additional 0.1uF capacitor from Vcc to GND for each driver to avoid high current peaks for the voltage regulator and using a separate voltage regulator for the drivers can help.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Why 1MHz? You have 128 channels and 8 bits per channel. You need to update it 60 times per second (in European countries: 50 times per second). This results in a data rate of 61,440 bits per second.

I would use RS232 with 115,200 baud, which is more than enough, including some control bytes and checksumming. If it is a long line, use RS485, with converters at the PC side, maybe an electrically isolated RS485 driver.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

I've embedded my comments below in-line.

- John_H

Nevo wrote:

I don't think the practice is questionable, myself. The I/Os can individually source and sink 25mA easily. The total current is not a problem either given the total current handling capability of the device. If you use external current-limiting resistors for each optoisolator, the voltage drop in the FPGA is small. Driving the cathode is slightly better than the anode for voltage drop but the IBIS model suggests the voltage drop for 7mA is less than 0.1V typical for the LVCMOS33, 8mA, slow slew rate driver. 128 channels of 7mA at 0.1V drop is only 90 mW dissipated in the I/O drivers (assuming I got all my information right this weekend morning).

The output capacitance range for stability for the ST part is shown in graphs in figures 18 and 19 in the datasheet:

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You might find a better discussion on the caps in the national data sheet (device also available on digikey, LM1085IT-3.3)

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or see more capacitor discussion in the more expensive national part

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Personally, I'm a little wary of such a high ESR specified in the ST datasheet for stability but I've been working mostly with switching regulators over the last several years. Beware of "Low ESR" bulk caps since the LDO regulators need a measurable value of ESR.

Forget about total capacitance for the LDO, think only of the bulk value: the tantalum. Going with 12 1uF caps around the FPGA would give you greater than the target 10 uF but your LDO will probably go unstable; unless, perhaps, you have a large input capacitance from ceramic chips per the last national semi device's capacitor discussion. Tantalum caps are probably the way to go, just be sure to use a voltage much larger than you need. The 16V tantalums I used for my 12V circuit with well behaved ramp-up times showered sparks on the first power-up a decade ago. Nice black pit left in the board. Over-rate the tantalum caps by at least 100% on operating voltage. The over-rating isn't required for ceramics.

The time it takes the regulator to start turning back the tide of capacitor drain is only a couple microseconds with 10 us or so for full regulation. The sheet shows the behavior for a large transient. If you turned on one channel each 4 MHz clock, you'd have the .896A transitioning-on smoothly over 32 us and the change in the output voltage for that extreme swing would probably be under 25 mV.

Unless your power and ground planes are *very* close together, there isn't necessarily a big advantage, but.... You can supply your 3.3V on the bulk of the power plane and have a 1.5V "island" under the QFP that you feed with the single 50-mil trace. I wouldn't recommend only traces to the VCCINT pins.

There are 12 VCCIO pins and 12 VCCINT. Please read up on what to do with VCCA if you're not using the PLLs (...those funny Altera parts). Do you need 24 caps? Probably not. You're not handling huge transients of current at high switching frequencies. Tie 8 to the 3.3V plane and 4 to the 1.5V plane for a nice distribution across the four sides (unless you'd like to use 24, of course). Or 4 and 8. Your requirements aren't strong here. Given the sensitivity of LDOs to too much ceramic capacitance, I'd stay away from the 1uF parts even though some engineers like "bigger" if the price is the same. Varied values are also not needed in your case since the 4 MHz switching frequency won't build up nasty harmonics with the limited current steps you produce. In your case, simpler is probably better. Caps soldered at the periphery of the QFP can connect easily to a plane inside the part outline or a plane outside the part outline.

A 32 bit counter at 4 MHz will give you a 1000 second range where you only need 1/120 s, isn't it? You can make your counters any size. Minor note.

The Cyclone doesn't have LVDS receivers, does it? LVDS is probably overkill. If you supply a good ground through your cable, you should be able to get by with LVCMOS style signals. Think of the ribbon cables in your computers - they didn't start off with LVDS. If you get LVDS for free or just want to do it, go for it! I love LVDS over cat5, but my data rates are about 500 Mb/s. You could still use cat5 with 1 pair wired for data (both wires, same signal) and one for clock with the other 4 wires supplied for ground.

Since you state "LVDS input pins," are you not in the Cyclone-I series of parts? If the receivers are there, the LVDS is free, but make sure the LVDS inputs are compatible with the 3.3V I/O banks. You still want a common ground between the two boards for common-mode reference even if you use LVDS.

Note that your dimming may not be linear since your lights are driven by AC voltage. You can communicate a value and just have that value compare against the counter. There are many ways to skin this particular cat, just keep the linearity in mind.

VCCIO and VCCINT both need caps.

I love these personal projects.

Reply to
John_H

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