Xilinx DDR2 Interface

At the risk of stating the obvious, it is a reset pin.

Cheers, Jim

But why is it necessary? Doesn't the normal FPGA configuration process reset the DDR2 interface? I can't find any info on how to use this input.

The DDR memory itself will likely require an initialisation sequence - this is certainly the case for SDRAM - I would imagine this signal tells the controller to perfom this initialisation.

This is off-topic, but the "_N" probably indicates that this is an active-low signal; I want to know why we still have new designs with active-low signals. Is it 1982? Does the MiG only work on TTL parts? -Kevin

MIG creates a wrapper for the memory code. You don't need to route the reset input to a pin of the FPGA. Most designs just use a simple startup circuit (a few flip-flops initialized to 1 during config in a shift-register configuration) unless the FPGA needs to wait for some external event to start up.

What you say makes sense and seems to agree with the signal description in the MIG User Guide. I'm still curious as to why MIG assigned the signal to an FPGA I/O pin. Maybe there was some option I got wrong when running MIG.

Thanks for your response!