Field-Programmable Gate Arrays

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ATF750 for Proteus

Hi! I'm looking for the Atmel ATF750C library for Proteus but I'm unable to find it on both Atmel & Labcenter sites. Do...
4 comments posted 18yrs
posted by newsnet
4 comments posted 18yrs posted by newsnet

ANNC: Digital Power Management Webcast

Lattice is holding a webcast today Thursday, April 24th, "Digital Power Management for Analog Supplies." The presenter...
0 comments posted 18yrs
posted by bart.borosky
0 comments posted 18yrs posted by bart.borosky

ACTEL FPGA static timing analysis

I am using actel 1280 FPGA. How to use the Timer to detect set up violations arising due to clock skew between two regis...
0 comments posted 18yrs
posted by shyamsundar.sriram
0 comments posted 18yrs posted by shyamsundar.sriram

HydraXC + EDK

HI, I'm struggling with an EDK project and a HydraXC here. First of all I can't get the Hydra to work. I loaded a sampl...
5 comments posted 18yrs
posted by u_stadler
5 comments posted 18yrs posted by u_stadler

video stream transfer via UART and Bluetooth in FPGA

I need to send video stream over a bluetoth link , case 1 ) the video lise is some format (suggest a easy format) in CF...
4 comments posted 18yrs
posted by narendra.sisodiya
4 comments posted 18yrs posted by narendra.sisodiya

superscalar processor design

Hi I am just wondering if somebody has some good sources for a superscalar processor implementation in VHDL? I have fou...
0 comments posted 18yrs
posted by Peter
0 comments posted 18yrs posted by Peter

FPGA comeback

Hi I want to get into FPGA design after long time I was out of it. I did some work with ALTERRA long ago . I mainly did...
7 comments posted 18yrs
posted by therightinfo
7 comments posted 18yrs posted by therightinfo

Verilog state machines, latches, syntax and a bet!

Hi, A colleague and I are having a friendly debate on coding state machines in Verilog, targeting synthesis for FPGAs....
9 comments posted 18yrs
posted by xjjzdv402
9 comments posted 18yrs posted by xjjzdv402

10.1 EDK - How can I create a user library in SDK?

Dear experts, I may need to build a few user libraries for PPC and MBZ targets, the libraries would be hardware indepen...
0 comments posted 18yrs
posted by andrew.nesterov
0 comments posted 18yrs posted by andrew.nesterov

the order in which some switches are turned on

Hi all, I have an array of N switches . Initially all are OFF. Somebody turns them ON in some order. It is possible tha...
4 comments posted 18yrs
posted by laura.brandusan
4 comments posted 18yrs posted by laura.brandusan

Can somebody help about Period Timing Constraints

Hi all, I don't understand is there any the relationship between the value of period constraints and my input clock? Fo...
1 comments posted 18yrs
posted by songrise
1 comments posted 18yrs posted by songrise

FPGA Verilog state machine lock up

Hello, I am using Verilog to program a Xilinx FPGA. The program is basically a state machine with at least 32 states. T...
1 comments posted 18yrs
posted by neena.nambiar
1 comments posted 18yrs posted by neena.nambiar

Xilinx is cancelling the Virtex-E XCV1000E-FG860

Xilinx is canceling the Virtex-E XCV1000E-FG860. We are currently shipping a product that uses 13 of these chips on 4 d...
13 comments posted 18yrs
posted by alan
13 comments posted 18yrs posted by alan

Need a few Xilinx Spartan FPGAs

Hello, Does anyone have a few XCS30 -3TQ144C FPGAs around, or know a distributor who will sell in small quantity? I nee...
0 comments posted 18yrs
posted by elson
0 comments posted 18yrs posted by elson