As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't understand and really i need help to advance in my project :
- first how we can prove that really the AES 256 (cbc mode) is used to crypt the Bitstream +> is it possible to know this by taking advantages from the .rbt file ? starting from the .rbt file for encrypted design how can i extract the IV (init vector) , and from wich part exactly start the enryption ? after the header information ?
-second , where exactly the key is stored ? articles said " the key is stored in dedicated memory" ... the key is stored some where in the surface shown by FPGA Editor or elsewhere ??
-third , what is the effeciency of the side channel attack to break AES 256 ?
regards joe