How to instantiate macro in verilog

Dear all,

I've designed a macro, and put "ring.nmc" file in my project dir. In my verilog module file, I wrote ... ring r1(.en(en),.ro(ro)); ... to instantiate ring macro, but failed.

Any one could give some hint?

Thank you!

Reply to
Haile Yu (Harry)
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Can you copy the exact error message here? That may give some hint?

Cheers, Jim

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Reply to
Jim Wu

If this is a ring oscillator, you may be having problems with the tools stripping away the logic. -Kevin

Reply to
Kevin Neilson

Hi, Kevin is right, also I use macros: declared as black box and write their "portlist followed by endmodule " in a "macro_name.v" file in the working directory.

Hope this helps, /MH

Reply to

I'm not sure what you mean, and your syntax is unusual: I think a "macro" is a software term. Anyway, I'm not sure what the issue is here, but if you are trying to make a ring oscillator, one problem is that the synthesizer and mapper try to strip it away because it's a combinatorial loop and makes no sense from a logical standpoint. So you might have to put some sort of "keep" directives to prevent this. -Kevin

Reply to
Kevin Neilson

n- Hide quoted text -

Hi, I will try to explain my previous post:

while making an instance of a macro file, as described by OP,I use following syntax:

//-----------------------------------------------------------------// ring r1(.en(en),.ro(ro)); //synthesis black_box

Make a new file in editor as:

module ring ( en, ro );

input enable; output ro;



In my knowledge, making a file as above avoids synthesis error of unavailability of file. And declaration of instance as a blackbox would make the tool search for a netlist of the macro.

I may not be following the exact steps but it actually works for me while playing with Bus Macros of Dynamic Partial reconfiguration or working with EDN/NGC files with no verilog RTL.


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