Survey: FPGA PCB layout

The best way to get good pinouts is to finish a working prototype of the hdl code before making the board. I let place and route make the first cut unconstrained and then clean up from there.

Not me. Whoever does this, should do it all day long, every day.

The first pass might save some money, but by the time you have a working board you will be in the hole.

That is correct.

-- Mike Treseler

Sure wish there was a slick way of doing FPGA pinouts. I usually use graph paper and figure out the FPGA pinout to other parts to minimize routing snarls.

I do pcb layouts on my own and other folks designs. Our boards have high-speed routing, switching power supplies, and high-gain analog stuff; sometimes all on the same board. Unless the service bureau has someone who understands how to lay out such circuitry and place sensitive analog stuff near digital junk, it is more trouble to farm out than do it yourself if you want the board to work on the first cut.

Doing your own layout will take a lot of learning to master the PCB layout program and what your board vendor can handle. It will take 5 to 10 complicated boards to become mildly proficient at layout. I don't know about saving cost. Your time may be better spent doing other activities rather than learning about layout and doing the layouts. The upside to doing your own layout - you control the whole design from start to finish. If you have a challenging layout, you'll have a much higher probability of having a working board on the first try which has hidden savings (getting to market earlier

Or find a good layouter and develop a long-term business relationship. My layouter knows just from looking at a schematic which areas are critical. He's a lot older than I am and that is probably one of the reasons why his stuff works without much assistance from me. Nothing can replace a few decades of experience.

Yep, that's why I usually do not do my own layouts. Occassionally I route a small portion of a circuit and send that to my layouter. No DRC or anything, just to show him how I'd like it done.

--
Regards, Joerg

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Dave wrote:

Hi Dave, I layout my own PCBs. Unlike Mike T., I don't let the FPGA tools pick the pinout. That said, it is important to consider carefully consider nets which might have tight timing, e.g. clocks. I reason that there is a lot more flexibility in the FPGA routing than on my PCB, and it's cheaper, so I can save most time and money by being flexible in the pinout. I set the banks the nets are to go on, and firm up the detailed pinout by swapping pins on the FPGAs banks during the PCB layout process. You need some experience in what your HDL code is gonna look like to be able to do this, but there you go. If you are adept at FPGA work, you'll find learning a PCB layout tool is a piece of cake. I also use laser drilled microvias from layer 1 to 2, which make the layout of big BGAs easier and saves layers. SI is easier also. The price is usually less this way; the layers outweigh the via expense. You don't need buried vias, IME. Some of my FPGA buddies and I have had bad experiences with contract PCB people. Sometimes they are knowledgeable and talented, but sometimes they are dogmatic idiots, and sometimes they are useless. If you go the contract route, it's important to closely monitor what they get up to so you find out early doors which type they are. Like you and Mike say, it depends a lot on your experience. If you've worked closely with your layout guys in the past, that'll be a big help to you. For sure, there's more than one way to skin a cat, but I enjoy PCB layout. YMMV, good luck with it. Cheers, Syms. p.s. One benefit to laying out the PCB yourself is that it can help you spot stupid mistakes in the circuit as you go. It forces you to look very closely at the layout.

Hi Joerg, That's a excellent middle way. Cheers, Syms.

Depending on your PCB layout (and schematic capture) tools' capabilities for defining constraints on pin swappability, you can develop symbols that constrain IO pin swapping to meet the needs of the design and/or FPGA. For example, we have symbols for FPGA's that limit IO pin swapping to the same bank and other banks powered from the same voltage rail. We lock down critical pins (global clock inputs, etc.) and we have to "seed" the banks with their voltage assignments, but after that, we are often able to let the PWB tool auto-swap the FPGA pins, and then clean that up in layout. Then we feed that pin out back to the FPGA design tools, and make sure we can place and route the design in the FPGA while meeting timing. This is often with a preliminary version of the FPGA code, but with relevant IO structures in place.

Andy

Hi Andy, Do you use PADS I/O designer?

Also, have you ever found that the PWB tool swapped pins that prevented your FPGA code meeting timing? I never bother testing, because it always does. I'd be interested in any counter examples you have. Thanks for your post, Syms.

Dave

We are slightly unusual in that we started as FPGA design house and now probably better known for our boards even though we do an awful lot of internal FPGA design still. A lot of board layout is just common sense. Having a plan of how it all fits together - not just placement but routing runs between chips usually pays great dividends.

Having someone who understands both the FPGA and the pcb layout is usually a great advantage as it allows tradeoffs to be made easily and generally ends up with with a better board. Swaping I/Os as you layout will give a much better results.

That all said we are still learning on our pcb design skills even after producing development boards for nearly 5 years and I can still say generally that every new board we do is technically better than the previous one we did.

Your first board will probably take a long time especially if it as in any way complex. Our first development board (Broaddown2 for the interested) that we released took about 800hrs of man effort. We would do that same board now in probably less than 1/3 of that time now.

So in summary you have the difficult decision whether to invest time in learning the trade, making mistakes along the way, and possibly getting better boards versus the direct cost of using someone experienced and reducing the risks of a good enough to ship first layout. Very few people achieve boards that are good enough to ship as practical production boards as first revisions and if you do that you are doing well. Wire mods etc in production cost lots. I'm know of some designs done by customers themselves that have gone to 7 versions due to mistakes in layout. That's not cheap and really hits timescales. I'm proud to say my team have delivered over 50% of our development boards to production, to ship at 1st issue, but that is definately unusual in boards of that level of complexity.

Board can be an enjoyable task but it's not for the impatient.

John Adair Enterpo> Does anybody out there have a good methodology for determining your

I agree with Joerg. Good high speed or mixed signal PCB layout is a career choice, and we electrical engineers already chose our career. A good layout requires someone who understands not just the software package, but the details of how the manufacturing operation is going to proceed, what the limits of the processes are, what the assembly operations require of the board, and is anal about things like footprint libraries and solder mask clearances and a thousand other details that I'm only partially aware of. The more complex your design, the more critical these things become.

I have two good local outfits for farming out boards. For complex stuff, they know I'll come to their place and sit next to the designer for a good bit of the initial placement. While we are doing placement, we are also discussing critical nets, routing paths, layer usage, etc. That gives us direct face to face communication and avoids spending lots of time trying to write/draw everything in gory detail (which gets ignored or misunderstood a lot of the time). That investment pays big dividends in schedule and board performance.

Don't be fooled by the relatively low cost of the software. That's not where the big costs are.

I once laid off my entire PCB layout department and sent all the work outside, because although my employees all knew how to use the software, none of them could tell me what their completion date would be, or how many hours it would take, and they certainly weren't interested in meeting schedules. The outside sources would commit to a cost and a delivery date. And we already knew they could meet our performance objectives. Fixed price contracts are great motivators. Missing an engineering test window, or slipping a production schedule because of a layout delay can be enormously expensive.

Of course, if I had let my engineers do their own layouts, the motivation would have been present, but the technical proficiency would not. How proficient can anyone become if they only do layout a few times a year? Also, on many projects engineers use the layout period for other important things like documentation, test procedures, writing test code, etc. Doing your own layout serializes these tasks and will stretch your schedule.

So my advice is to keep doing what you have been doing. Its far more likely that its the cheapest approach, even though you occasionally have to write a big check.

Steve

I tend to agree with the 'farm-it-out' crowd. Unfortunately, my current employer doesn't want to work with my previous layout people, so I've been trying to search for a new partner. I've found plenty of board fab and assembly places, but not so much on the layout. It made me think that the rest of the world did their own layout. The opinions look pretty split from the replies here, maybe it comes down to how many times you do a layout each year, and how much you enjoy that sort of work. I definitely think it's something you have to do fairly often to keep your chops up.

Andy, I'd also like to hear more about your pin-swap FPGA design flow

- what tools do that? Also curious about any timing issues that have been caught after the pin-swap.

Thank you all very much for the info. If any of you find yourself in the Baltimore area, I owe you a crabcake sandwich and a beer.

Dave

Some of the PCB software vendors have lists on their web site of independent consultants and layout houses that use their software. I went on the Mentor site and found zillions of layout people.

-Jeff

I think what you're seeing is that fact that, by sheer volume of products, guys doing relatively low-speed digital stuff completely dominate those doing very low-level analog, RF, microwave, or truly high-speed digital. In the former case, it just doesn't really matter that much how you layout the board. Sure, there are definitely better ways and worse ways, but even up to clock rates pushing 100MHz, for digital stuff I think you can give a guy about an hour of education and he'll be able to make boards work just fine.

Another point to keep in mind is that there's a significant difference between being able to design a board well when you're talking relatively small volume production for high-end commercial or military customers where you can afford to just toss in some extra layers and pay for blind or buried vias or tigether tolerances if you're at all unsure of how well your layout skills really are vs. designing a complex board for highly cost-competitive mass-markets. The later requires a lot of skills that are anything but what is commonly taught! (E.g., typically at tech seminars you'll hear people preaching, "throw in a ground plane!" -- an action that saves many an otherwise broken design, but one which might not be possible if your competition has already figured out how to live without one.)

I'm a big advocate of giving "technical interviews" to would-be PCB layout guys based on what your needs are. If you're doing, e.g., RF or high-speed digital design, ask them how line impedances change with changes in board and trace dimensions, what near-end and far-end crosstalk look like on a scope, what they think about splitting up ground planes, how they'd route some simple circuits, etc... Usually you can find out pretty quickly what their skills are whether or not they're adequate or if they'd need a bit more hand-holding... which could be fine too, if you have the time and the price is right.

It's a common feature in most PCB tools to allow pin (and gate) swapping based on the component's library entry being set up to designate which pins and gates are "swappable." After doing so, most of them will produce a simple ASCII "was-is" text file that list the old pin name and the new one, which can be imported back into a schematic capture program or used to update your FPGA place & route constraints. (PADS will do all this, where Pulsonix unfortunately does pin & gate swapping quite nicely but will only update a Pulsonix schematic "directly" rather than providing you with the option to generate a was-is file.)

---Joel

Not anymore. Part of my daily bread is earned salvaging designs where someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 anymore, today's logic chips are fast. Some like the tiny logic chips swing their outputs within very few nanoseconds. Then some unexpected weirdnesses show up. Everyone thinks it's software but in reality crosstalk has manifested itself. Other times the moment of truth cometh at the EMC lab when a thick forrest shows up on the spectrum analyzer.

And don't split that plane. But yes, often one has to make do with two-layer phenolic. That is often true art.

BTW does that little switcher work?

[...]

--
Regards, Joerg

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OK, ok, good point. Doesn't someone now have a logic family that's purposely been slowed down due to this "problem?"

From Thomas Lee (Stanford) in "Planar Microwave Engineering":

In extremely low-cost consumer devices (e.g., toys, pocket radios, etc.), an even less expensive board material is not infrequently encountered. Phenolic is often a caramel brown, typically has an "organical chemical" odor, and is remarkably lossy. Although phenolic is occasionally used for RF toys up to

100MHz, it is totally insuitable for serious applications. It is mentioned here simply to answer the question: "What is that cheap, malodorous board made of?"

:-)

I know, I know, he's living in an ivory tower a bit, but he is one smart cookie.

I've had that board back for about a week, although I haven't actually tested out the switcher yet since the DSP guy isn't interested in working with the new (digital) board until the new RF board comes back (and gets tested) as well, which is still a couple weeks out. (There's this "Big Tester Board" that's needed to test the RF board and said BTB has spent something over a week bouncing around engineering getting tweaked/fixed/etc... we'll be paying a premium to actually get it fabbed in time to start testing RF boards at this point, unfortunately :-( .) I can and probably should just put a dummy load on the switcher, turn it on, and see if there's any obvious problems before the DSP guy starts looking at his clock jitter. Tomorrow sounds like a good day for that...

---Joel

There used to be but it's gone. They also had really high threshold voltages and stuff.

Errr, well, those sure sound like ivory tower statements. For some reason all the phenolic I ever used has never smelled. Unless something blew up on there, of course, but then FR4 will also let off a nasty stench. The new stuff looks amazingly similar to FR4, not dark brown. Remarkably lossy? Nah. I have proof to the contrary right here in the garage (if it's still there), a VHF/UHF TV splitter and 60ohm to 240ohm transformer where the UHF part is almost completely done in microstrip. Yes, microstrip on phenolic. There may be a fraction of a dB here and there but on short stretches that hardly matters. Usually those things are for outdoors so it's lacquer coated anyway. Phenolic is somewhat hygroscopic so you have to watch out for moisture.

Totally insuitable for serious applications? Oh man. Let's see, what have we here? A 418MHz transmitter, several matching networks, a UHF receiver ... all on phenolic.

Sometimes I wish that professors had more nose-to-the-grindstone industry work under the belt. I mean real design work where cost is a big factor. Otherwise they are going to tell students they should use Rogers for just about everything ...

That would be good. Gives you a head start just in case there is a surprise ;-)

--
Regards, Joerg

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What's the brute force method? We preassign most fpga pins for clean, no-crossover routing to other chips. We discuss the general issues, especially placement, with our pcb layout guy and he actually decides which pins go where. Then he back-annotates the schematic and gives us a file we can use to create the fpga pin constraints file. Sometimes bank issues complicate the process, but it works pretty well.

We'd never farm it out. We do critical mixed-signal stuff, and need to be near our layout guy constantly. He puts up a version on our server daily at least, and we keep an eye on progress. And we have a lot of mini-meetings to change the rules as needed. Besides, we have evolved some styles (and libraries!) that we couldn't very well transfer to a service bureau. PCB layout is too important to farm out.

For really critical stuff, sometimes I'll take over and route that part of the board myself. It's just too hard to communicate exactly what I want.

John

Multi ghz RF+matching stuff, analog and some digital will work on an FR4 derivative.

Don't forget rogers is not perfect , intolerance to flexing and intolerant of poor soldering techniques.

>

In Altium Designer I use the incredibly useful "subnet jumper" feature for BGA's. The procedure goes something like this:

1) Fan out all the required FPGA pins first (automatically or manually) to just outside the chip boundry. (leave several diagonal entry paths for core and other power flood fills to get in) 2) Fully route all non-pin-swappable pins and other critical lines. 3) Ensure any other parts placements are near any required FPGA pins or block features you think you might need. 4) Route every track just short of the fanout tracks 5) Hit the "add subnet jumper" feature and it finishes the tracks and does all the pin swaps for you and updates the schematic.

Probably needs a picture or two to explain it best though...

The great part about subnet jumpers is if there are timing or other problems you can just remove the subnet jumpers and add/edit tracks and pins as needed and then replace the subnet jumpers. Only takes a minute or two.

Dave.

I always farm out the layout. At the most I do a mock layout of, say, a hotrod RF amp area and send it to the layouter. During layout Gerbers go back and forth all the time, sometimes in 15min intervals. Once my layouter had to be in Vermont during the job, no problem. Crunch time, he worked into the night, I had a laptop in the living room and whenever it beeped I'd go into the office, check the Gerbers and reply.

Also really nice was a company overseas. I only had to check some critical areas during layout (which was done over there). They used a subversion system so a scattered team could cooperate without accidentally stepping on each others files. It was almost as if their server was here in the basement.

Yes, for really hot stuff it's good to sit next to each other. In the past I'd driver over there and me, the layouter and his cat would do the tough parts of the layout together. Unfortunately his cat has passed away by now.

--
Regards, Joerg

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