Field-Programmable Gate Arrays

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Virtex4 DCM doesn't work unless freezing cold

Hi everyone, We've been shipping a Virtex4 FX20 based product for a few months now with relatively few problems. Howeve...
5 comments posted 18yrs
posted by msn444
5 comments posted 18yrs posted by msn444

what's the difference between .rba & .rbb files ?

Hi , Bitgen generates as readback files ( .rba & .rbb) , but wich one contains exactly the data that is configured in th...
1 comments posted 18yrs
posted by bamboutcha9999
1 comments posted 18yrs posted by bamboutcha9999

XUPV2P and EDK 10.1

Hi all, I'm glad to see that the XUPV2P board is now supported by EDK 10.1. However, setting the MPCM memory controller...
1 comments posted 18yrs
posted by ascgroup
1 comments posted 18yrs posted by ascgroup

XCF02S not seen in the JTAG chain

Hello all, First of all, I understand the best way to have a solution is to start a webcase and I am doing it right now...
4 comments posted 18yrs
posted by aee
4 comments posted 18yrs posted by aee

Hand-editing xilinx.sys

I have a systemACE based dev. platform for Virtex-5 and copy my ace files by hand from my linux system to my CF card. E...
0 comments posted 18yrs
posted by davemacadam
0 comments posted 18yrs posted by davemacadam

PPC + APU + FSL + Xilkernel Problem

Hello, I currently working on a project in EDK 9.1. I have a PPC system with a custom peripheral the is connected to th...
0 comments posted 18yrs
posted by u_stadler
0 comments posted 18yrs posted by u_stadler

Style for Highly-Pipelined State Machines

I'm designing another FSM and I've run into the problem I always have when trying to pipeline them for high-speed design...
9 comments posted 18yrs
posted by kevin_neilson
9 comments posted 18yrs posted by kevin_neilson

Functional Simulation of Virtex-4 Block Memory

I am doing my first FPGA design. The design uses VHDL source with a few Xilinx cores (a Virtex-4 device will be used)....
16 comments posted 18yrs
posted by charles.elias
16 comments posted 18yrs posted by charles.elias

floating point and logarithm in vhdl+xilinx

Please sombody help me. I am trying to write a vhdl code and i need to use floating point arithmetic and logarithm. I h...
1 comments posted 18yrs
posted by digi.megabyte
1 comments posted 18yrs posted by digi.megabyte

Chirp generator / CORDIC algo ?

Hello, I am on a project of developping a chirp generator on a FPGA. Reading from the internet I learned that the CORDI...
10 comments posted 18yrs
posted by XSterna
10 comments posted 18yrs posted by XSterna

Virtex4 PPC405 - FPU problem

[first posted on comp.arch.embedded] ML403 - Virtex4 XC4VFX12 - PPC405 - Xilinx EDK V10.1 Hi, I have a working PPC405 d...
0 comments posted 18yrs
posted by noemail
0 comments posted 18yrs posted by noemail

parallel port using XSA-50

Hello All, I am in need of a tutorial for parallel port programming on the XSA-50 board. Can anyone suggest a great tut...
0 comments posted 18yrs
posted by uraniumore235
0 comments posted 18yrs posted by uraniumore235