Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Could someone tell me NIOS II/MB performance on this benchmark?
I trying to get a feel for how the performance of my (so far unoptimized) soft-core stacks up against the established competition, so it would be a great help if people with convenient access to Nios...
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16 years ago
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Debounce in Verilog?
Hi guys: I'm using a Xilinx FPGA for an application and I'm having trouble with an input square wave that has a little bounce at its transitions. At this stage of the game, it would be difficult for...
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16 years ago
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understanding xilinx silicon revisions (does ES come before CES4, etc.)
In trying to fix a bug with Ethernet MAC/phy operation, I came across AR 24494 which mentions "silicon rev CES4 or later". How can one determine the silicon rev? I have two different parts marked as...
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16 years ago
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Darnaw1 Schematics
Schematics are now available on our website for our low cost development board Darnaw1. These and other materials for this board are linked on John Adair Enterpoint Ltd.
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16 years ago
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How to embed time and date in Xilinx FPGA?
I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into my Verilog code. I would like to automatically call that...
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16 years ago
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what's next?
Hello Group, I have done a couple of small fpga projects with verilog. I am looking for some follow-up fun projects to increase my experience and exposure to FPGA/verilog? I am thinking of interfacing...
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16 years ago
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Quatech SPP 100 PCMCIA to Parallel Adapter for FPGA Board for Sale
Just in case anybody interested, I am selling Quatech SPP 100 PCMCIA to Parallel Adapter. This is the latest version of SPP 100 (Rev. H) and compatible with 3.3V and 5V PCMCIA slot. I have tested it...
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16 years ago
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how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY
i v some questions about the encrypted bitstream in the Virtex 5 , hope someone could answer me : 1* As we know the algorithm used to encrypt data in Virtex 5 ( AES 256 cbc ), can i edit by myself an...
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16 years ago
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CRC algorithm
is someone has the code of CRC (cyclical redundancy check) that xilinx use in the bitstream ? is it a simple CRC ( the XOR of words ) ?
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16 years ago
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Virtex-4 inrush power-on current
I am replacing a V4FX20 chip with a V4FX40 on a board. I am a little bit concerned with the power-on requirements of the bigger chip. The existing core voltage power supply is designed for 1A. The...
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16 years ago
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How to arrange these SRL16 in a straight column
Hi, I want to put a column of independent SRL16 in a Virtex 4 xc4vlx15 continuously. For even number, there is no problem. For odd number, I cannot make them continuously even though these SRL16s are...
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16 years ago
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Spartan3 "commercial" temperature range
Spartan3 family has two operating temperature options, "commercial" and "industrial". This usually means 0/+70 °C and -40/+85 °C, but in Xilinx case the ranges are actually 0/+85 °C and -40/+100...
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16 years ago
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Timing closure problem --- how to make the QII fitter smarter
Hi there, I am trying to get a design passing the timing to run at 622.08MHz clock on a Cyclone III device. All the critical paths has been pipelined so there is only one level of combinational logic...
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16 years ago
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PLB Master Example
Hi all, Im building a custom IP that needs to write data to DDR Ram on the XUPV2P board (Virtex 2 Pro). Basically need to dump data from a 16kb BRAM to DDR in burst mode. Data width is 64bits, which...
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16 years ago
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V5, EMAC simulation problem, when 4 EMACs are used together (ISE 10.1, ModelSim 6.3d)
Hi there, I wanna use in my design 4 EMACs. I have used CORE Generator to generate 2 Virtex 5 Embedded Tri-Mode Ethernet MAC wrappers 1.4 (each contains 2 EMACs). In fact, they have the same...
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16 years ago
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