understanding xilinx silicon revisions (does ES come before CES4, etc.)

You are basically right. Your second part is the full commercial silicon, which is also known as CES5. Your first part is probably CES1. I guess at that point Xilinx didn't have plans to release different versions of engineering samples, so they didn't include the number in the marking. Starting with CES2 the number was included in the marking.

/Mikhail

Jeff,

Yes, that is the date code, the XX week of the YY year (for YYXX code)

Note that the next line has the stepping code (if used) at the end).

Note that after CES4 comes stepping 0, then stepping 1, so the third line has a 1 at the end if the production stepping is 1 (nothing if it is a step 0, or the first production mask set).

So, the second part is a stepping 0, whereas the first part is before CES1, 2, 3, or 4 markings, and is the very first engineering samples, plain ES, before we even had characterized C grade, or I grade.

At least, that is what I am interpreting from the above answer records, and what I recall about V4 FX (which, quite frankly, was a terrible embarrassment. We have all vowed to never make those mistakes ever again!).

So, the first marking you ever see is ES, always the lowest speed grade (effectively, no real speed grade has been verified yet), followed by CES, or IES grades, followed by (first) production step 0 (no number at end of third line), followed by subsequent steppings to fix subsequent errata that may be discovered.

Austin

MM,

Not sure is ES == CES1 (it may, or may not, be the same mask set). As soon as we start testing for the speed grade, we add the C to the ES.

Before that, the ES alone indicates the part is untested at temperature.

Austin

Jeff,

CES4 only applied to MGT's.

No MGT's on FX12, no CESx markings at all.

You have the ES first mask, and the production step 0 mask parts.

No CES4 (pre or post).

Austin