Latest threads in Field-Programmable Gate Arrays

Could someone tell me NIOS II/MB performance on this benchmark?

I trying to get a feel for how the performance of my (so far unoptimized) soft-core stacks up against the established c...

5 18yrs

tommy.thorn

5 18yrs tommy.thorn

Debounce in Verilog?

Hi guys: I'm using a Xilinx FPGA for an application and I'm having trouble with an input square wave that has a little...

4 18yrs

eromlignod

4 18yrs eromlignod

understanding xilinx silicon revisions (does ES come before CES4, etc.)

In trying to fix a bug with Ethernet MAC/phy operation, I came across AR 24494 which mentions "silicon rev CES4 or late...

4 18yrs

jcc

4 18yrs jcc

Darnaw1 Schematics

Schematics are now available on our website for our low cost development board Darnaw1. These and other materials for t...

0 18yrs

g1

0 18yrs g1

How to embed time and date in Xilinx FPGA?

I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can pu...

2 18yrs

freeagent.20.oracle

2 18yrs freeagent.20.oracle

what's next?

Hello Group, I have done a couple of small fpga projects with verilog. I am looking for some follow-up fun projects to...

0 18yrs

fei.liu

0 18yrs fei.liu

Quatech SPP 100 PCMCIA to Parallel Adapter for FPGA Board for Sale

Just in case anybody interested, I am selling Quatech SPP 100 PCMCIA to Parallel Adapter. This is the latest version of...

1 18yrs

u1000393

1 18yrs u1000393

how can i recover my unencrypted bitstream starting from encrypted one and knowing the KEY

i v some questions about the encrypted bitstream in the Virtex 5 , hope someone could answer me : 1* As we know the alg...

15 18yrs

swissiyoussef

15 18yrs swissiyoussef

CRC algorithm

is someone has the code of CRC (cyclical redundancy check) that xilinx use in the bitstream ? is it a simple CRC ( the X...

4 18yrs

swissiyoussef

4 18yrs swissiyoussef

Virtex-4 inrush power-on current

I am replacing a V4FX20 chip with a V4FX40 on a board. I am a little bit concerned with the power-on requirements of th...

13 18yrs

mbmsv

13 18yrs mbmsv

How to arrange these SRL16 in a straight column

Hi, I want to put a column of independent SRL16 in a Virtex 4 xc4vlx15 continuously. For even number, there is no probl...

2 18yrs

rxjwg98

2 18yrs rxjwg98

Spartan3 "commercial" temperature range

Spartan3 family has two operating temperature options, "commercial" and "industrial". This usually means 0/+70 °C and -...

5 18yrs

antonio12358

5 18yrs antonio12358

Timing closure problem --- how to make the QII fitter smarter

Hi there, I am trying to get a design passing the timing to run at 622.08MHz clock on a Cyclone III device. All the cri...

5 18yrs

Tommy.Ai

5 18yrs Tommy.Ai

PLB Master Example

Hi all, Im building a custom IP that needs to write data to DDR Ram on the XUPV2P board (Virtex 2 Pro). Basically need...

3 18yrs

raghunandan85

3 18yrs raghunandan85

V5, EMAC simulation problem, when 4 EMACs are used together (ISE 10.1, ModelSim 6.3d)

Hi there, I wanna use in my design 4 EMACs. I have used CORE Generator to generate 2 Virtex 5 Embedded Tri-Mode Etherne...

0 18yrs

vboykov

0 18yrs vboykov

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