Hi there,
I am trying to get a design passing the timing to run at 622.08MHz clock on a Cyclone III device.
All the critical paths has been pipelined so there is only one level of combinational logic inbetween registers and the fitter and synthesizer's setting has been tuned up for performance oriented according to the QII handbook. But still, some paths failed because of the propagation delay on the interconnections between LABs. I know I can set minimum delay constraints on these pathes to force the fitter place those LEs close together, but I am afraid some other paths will be placed apart on the chip and fail the timing. And I will have to put constraints on them and repeat this cycle over and over.
Now I am trying different fitter seeds to see if there is a lucky initial placement plan will work magically. But, are there any smart way to do this?
And, is there anyway to set the fitter to give higher priority in place and route to high frequency clock domains?
BTW, the design has already passed the timing for the fast timing model, but not for the other two slow timing model. Does that mean the design may work in some compilation, but may not work in some worse cases?
Thanks in advance and any advice will be highly appreciated.
Hua