Timing closure problem --- how to make the QII fitter smarter

Hi there,

I am trying to get a design passing the timing to run at 622.08MHz clock on a Cyclone III device.

All the critical paths has been pipelined so there is only one level of combinational logic inbetween registers and the fitter and synthesizer's setting has been tuned up for performance oriented according to the QII handbook. But still, some paths failed because of the propagation delay on the interconnections between LABs. I know I can set minimum delay constraints on these pathes to force the fitter place those LEs close together, but I am afraid some other paths will be placed apart on the chip and fail the timing. And I will have to put constraints on them and repeat this cycle over and over.

Now I am trying different fitter seeds to see if there is a lucky initial placement plan will work magically. But, are there any smart way to do this?

And, is there anyway to set the fitter to give higher priority in place and route to high frequency clock domains?

BTW, the design has already passed the timing for the fast timing model, but not for the other two slow timing model. Does that mean the design may work in some compilation, but may not work in some worse cases?

Thanks in advance and any advice will be highly appreciated.

Hua

Reply to
Hua
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What kind of design are you running at 620MHz ?

Rgds Andre

Reply to
ALuPin

Altera parts aren't my area of expertise, but I was curious about this question so I poked into the Cyclone III datasheet. You should have a look at Clock Tree Specifications, Table 1-18 in the datasheet, as the part is not capable of running this fast. The maximum clock frequency is 500 MHz.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Hi Andre,

It was an SERDES with 8B10B decoder/encoder targetting OC-12.

regards, Hua

Reply to
Hua

Yes Ed, we found out too. In fact, the bottleneck was the clock toggle rate for I/O pins. For LVDS the highest toggle rate was only 300+ MHz for this part.

Hua

Reply to
Hua

If you're targeting OC-12, the 622MHz is your bit rate. The 8B10B coder would typically be implemented at 78MHz.

If all you need ruinning at the highest rate is the serdes, you should be able to hand-place the LEs and IOs to get the best routing.

As for going beyond the 300 MHz limit, you will not be guaranteed to work under all conditions.

- John

Reply to
John_H

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