Debounce in Verilog?

By "software debounce in verilog" I assume you mean "hardware debounce in verilog". You need a trivially simple state machine and counter. While in state A look for a transition of the input square wave and pass it through. When a transition is detected clear the counter and go to state B. In state B, wait for the counter to count X states then go back to state A. X must be large enough to exceed the input bounce settling time. Don't forget to pass the input through a few flip flops to synchronize it if it is asynchronous to your high speed state machine clock.

You could also just sample the input at a period larger than the bounce settling time, provided you can live with the added latency and jitter.

-Jeff

I guess you mean a HW debounce?

will help you designing a HW debounce.

bye Thomas

I published a very simple solution to exactly this problem in XCell magazine #34, pages 54/55 I'll find you a URL tomorrow, when I am back at work. Or send me an e-mail to snipped-for-privacy@xilinx.com, and I'll send you the pdf file. Peter Alfke

Is your "input square wave" a clock to your FPGA design or a synchronous input? Asynchronous?

You find it difficult "to eliminate the bounce at the source" but we don't have a framework. The bouce is caused by the system which includes 1) source, 2) transmission line, and 3) termination. Do you have control over any of these parameters "at this stage of the game?"

- John_H