Field-Programmable Gate Arrays

Using SRL16

Hello, I am trying to synthesize a simple 8-bit delay line (delay of 10) on Virtex2 xc2v40-4cs144 FPGA. My objective is...

8 comments posted 18yrs

posted by partha.maji

8 comments posted 18yrs posted by partha.maji

Aldec Active-HDL 7.3 sp1 [stimulators]

Hi all. I'm brand new in fpga subject so please be patient :P My problem is about to use stimulatorin waveform. Well, e...

3 comments posted 18yrs

posted by Przemyslaw.Duda

3 comments posted 18yrs posted by Przemyslaw.Duda

Forking in One-Hot FSMs

Having two bits hot in a one-hot FSM would normally be a bad thing. But I was wondering if anybody does this purposely,...

14 comments posted 18yrs

posted by kevin_neilson

14 comments posted 18yrs posted by kevin_neilson

quick question

I have written a VHDL code to generate random numbers using a "process". I want to implement the same using function/pr...

14 comments posted 18yrs

posted by FPGA.unknown

14 comments posted 18yrs posted by FPGA.unknown

xilinx remote platform flash program

We are trying to develop a system that utilizes a Xilinx XC4VFX12 chip and platform flash. One of our main goals is to...

1 comments posted 18yrs

posted by bishopg12

1 comments posted 18yrs posted by bishopg12

Quartus v7.x fitting bug

Hello, Just trying this group as a bit of a last resort. I am currently working on a design that has identified a bug i...

3 comments posted 18yrs

posted by ian.barnes

3 comments posted 18yrs posted by ian.barnes

Virtex4 Output Pins during Configuration

Hi all, I have a problem with a Virtex4 FPGA, I'm using it to control a motor ... but during the configuration output p...

3 comments posted 18yrs

posted by gnemesis2001

3 comments posted 18yrs posted by gnemesis2001

Argh! Need help debugging Xilinx .xsvf Player (XAPP058)

I'm trying to get the .xsvf player in XAPP058 to work, but I haven't been able to do so. I have been able to do port.c,...

21 comments posted 18yrs

posted by rsg.uClinux

21 comments posted 18yrs posted by rsg.uClinux

Old FPGA question

Hi ! I have tried to enter the FPGA league for many years and I'm about to receive (at least ! the order was paid 6 mon...

12 comments posted 18yrs

posted by whygee

12 comments posted 18yrs posted by whygee

ARM Cortex for Altera available

Hi looks like ARM is easing up Cortex licensing, so it is no only available for M1 enabled Actel but pretty much ALL FP...

2 comments posted 18yrs

posted by Antti.Lukats

2 comments posted 18yrs posted by Antti.Lukats

NIOS II CFI interface

Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write so...

3 comments posted 18yrs

posted by bjzhangwn

3 comments posted 18yrs posted by bjzhangwn

co-sim for handel C with modelsim vs pure modelsim VHDL simulation

Hi, has anybody tried using co-sim for Handel C with modelsim? I managed to set up the co-sim environment, and got the...

1 comments posted 18yrs

posted by chrisdekoh

1 comments posted 18yrs posted by chrisdekoh

PCI Express Switch

Hi all, Wanted to verify a idea. Is is possible use Xilinx PCI express core in FPGA to use SMA ports for the physical l...

2 comments posted 18yrs

posted by shakith.fernando

2 comments posted 18yrs posted by shakith.fernando

Virtex4 DCM doesn't work unless freezing cold

Hi everyone, We've been shipping a Virtex4 FX20 based product for a few months now with relatively few problems. Howeve...

5 comments posted 18yrs

posted by msn444

5 comments posted 18yrs posted by msn444

what's the difference between .rba & .rbb files ?

Hi , Bitgen generates as readback files ( .rba & .rbb) , but wich one contains exactly the data that is configured in th...

1 comments posted 18yrs

posted by bamboutcha9999

1 comments posted 18yrs posted by bamboutcha9999