Latest threads in Field-Programmable Gate Arrays

need recommendation for PCB fab & BGA assembly vendor, I'm in SF bay area

Hi. Does anyone have recommendations for a pcb fab vendor and an assembly vendor ? Preferably the same vendor but ok if...

0 18yrs

rats

0 18yrs rats

FPGA Processor for Signal Processing ?

You find at the web and in books implementations of processors for FPGA =B4s and also processors like Picoblaze and Mic...

3 18yrs

HansWernerMarschke

3 18yrs HansWernerMarschke

Using SRL16

Hello, I am trying to synthesize a simple 8-bit delay line (delay of 10) on Virtex2 xc2v40-4cs144 FPGA. My objective is...

8 18yrs

partha.maji

8 18yrs partha.maji

Aldec Active-HDL 7.3 sp1 [stimulators]

Hi all. I'm brand new in fpga subject so please be patient :P My problem is about to use stimulatorin waveform. Well, e...

3 18yrs

Przemyslaw.Duda

3 18yrs Przemyslaw.Duda

Forking in One-Hot FSMs

Having two bits hot in a one-hot FSM would normally be a bad thing. But I was wondering if anybody does this purposely,...

14 18yrs

kevin_neilson

14 18yrs kevin_neilson

quick question

I have written a VHDL code to generate random numbers using a "process". I want to implement the same using function/pr...

14 18yrs

FPGA.unknown

14 18yrs FPGA.unknown

xilinx remote platform flash program

We are trying to develop a system that utilizes a Xilinx XC4VFX12 chip and platform flash. One of our main goals is to...

1 18yrs

bishopg12

1 18yrs bishopg12

Quartus v7.x fitting bug

Hello, Just trying this group as a bit of a last resort. I am currently working on a design that has identified a bug i...

3 18yrs

ian.barnes

3 18yrs ian.barnes

Virtex4 Output Pins during Configuration

Hi all, I have a problem with a Virtex4 FPGA, I'm using it to control a motor ... but during the configuration output p...

3 18yrs

gnemesis2001

3 18yrs gnemesis2001

Argh! Need help debugging Xilinx .xsvf Player (XAPP058)

I'm trying to get the .xsvf player in XAPP058 to work, but I haven't been able to do so. I have been able to do port.c,...

21 18yrs

rsg.uClinux

21 18yrs rsg.uClinux

Old FPGA question

Hi ! I have tried to enter the FPGA league for many years and I'm about to receive (at least ! the order was paid 6 mon...

12 18yrs

whygee

12 18yrs whygee

ARM Cortex for Altera available

Hi looks like ARM is easing up Cortex licensing, so it is no only available for M1 enabled Actel but pretty much ALL FP...

2 18yrs

Antti.Lukats

2 18yrs Antti.Lukats

NIOS II CFI interface

Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write so...

3 18yrs

bjzhangwn

3 18yrs bjzhangwn

co-sim for handel C with modelsim vs pure modelsim VHDL simulation

Hi, has anybody tried using co-sim for Handel C with modelsim? I managed to set up the co-sim environment, and got the...

1 18yrs

chrisdekoh

1 18yrs chrisdekoh

PCI Express Switch

Hi all, Wanted to verify a idea. Is is possible use Xilinx PCI express core in FPGA to use SMA ports for the physical l...

2 18yrs

shakith.fernando

2 18yrs shakith.fernando

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