V5, EMAC simulation problem, when 4 EMACs are used together (ISE 10.1, ModelSim 6.3d)

Hi there,

I wanna use in my design 4 EMACs. I have used CORE Generator to generate 2 Virtex 5 Embedded Tri-Mode Ethernet MAC wrappers 1.4 (each contains 2 EMACs). In fact, they have the same properties except of MAC addresses. I have written the top module where I used two generated components and made control for them. But after I started simulation, just one EMAC0 and EMAC1 generate txclient and rxclient clocks, EMAC2 and EMAC3 don't. I'm using in my project XC5VLX50T chip, which has

4 EMACs onto. It looks like EMAC2 and EMAC3 clock outputs go to undefined states after around 1 us.

Could someone tell me what's wrong there? or what is the right way to use 4 EMACs together?

Cheers, Vlad.

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