Field-Programmable Gate Arrays

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Xilinx IO drive level constrain

The IO drive level constrain specifies the drive level of a output signal .. if i am using LVCMOS33 with a drive level...
3 comments posted 18yrs
posted by kislo02
3 comments posted 18yrs posted by kislo02

Downloading external data file to FPGA

Hi I have a very basic question. Xilinx permits me to initialize Block RAM with an external data file. The thing I am j...
11 comments posted 18yrs
posted by FloXXX
11 comments posted 18yrs posted by FloXXX

Incremental compilation problem

Hi all, I am experimenting incremental compilation following the Quartus II software handbook. But somehow the fitter i...
2 comments posted 18yrs
posted by Tommy.Ai
2 comments posted 18yrs posted by Tommy.Ai

Xilinx XCL woes

OK, so I have this core I wrote which wants to read and write data to an= d = from SDRAM in a Spartan-E3 500 Microblaze...
1 comments posted 18yrs
posted by lists
1 comments posted 18yrs posted by lists

XILINX core generator question

Hi, Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to rea...
4 comments posted 18yrs
posted by Zorjak
4 comments posted 18yrs posted by Zorjak

using EXP connector of Spartan 3a board

We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We needed i/o pins to control motors and use various se...
3 comments posted 18yrs
posted by bisheshkh
3 comments posted 18yrs posted by bisheshkh

New Xilinx device package options for S3E & S3A

Thank you XILINX, you list new device package options for Spartan3E: (VQ100 for XC3S500E) http://www.xilinx.com/support...
2 comments posted 18yrs
posted by techseller
2 comments posted 18yrs posted by techseller

EDK 10.1 Map Error

Hi, Im getting the following error when trying to run the ML505 Standard IP Core Demo project from Xilinx. Im trying wi...
4 comments posted 18yrs
posted by raghunandan85
4 comments posted 18yrs posted by raghunandan85

XST 3.0 Xess Audio to Ethernet

Im a beginer in VHDL and i got some problems regarding Ethernet usage on XST 3.0 Board. I want to send audio trought et...
0 comments posted 18yrs
posted by pdrewa
0 comments posted 18yrs posted by pdrewa

Why this RLOC cannot be used two times?

Hi, I have encountered a strange problem. Because an adder is called many times by different width functions, I program...
0 comments posted 18yrs
posted by rxjwg98
0 comments posted 18yrs posted by rxjwg98

Xilinx LogicCore Direct Instantiation

Toolset: ISE/ModelSim_PE/VHDL I've been asked to modify one of my designs for another application so decided it was tim...
4 comments posted 18yrs
posted by krw
4 comments posted 18yrs posted by krw

CRC7 Input bits in Command and Response

Can someone confirm the SDIO CRC7 bits input for the 48 bits command and response and 136 response. For case 1 and 2 th...
1 comments posted 18yrs
posted by beky4kr
1 comments posted 18yrs posted by beky4kr

Microblaze Cache and FSL problem

Hi all , Out product uses the FSL bus to talk to a co-processor. So far I has the I and d cache for microblaze disabled...
0 comments posted 18yrs
posted by niladri1979
0 comments posted 18yrs posted by niladri1979