Latest threads in Field-Programmable Gate Arrays

impact / encrypted bitstream

Hi , i tried yesterday to configure my fpga with an encrypted bitstream . Using Impact 10.1 i didn't unerstand the way...

4 18yrs

swissiyoussef

4 18yrs swissiyoussef

signal value at power up

Here is my question/issue: say you have: y : out std_logic; signal x: std_logic; you don't assign any value to "x" but y...

7 18yrs

martstev

7 18yrs martstev

Xilinx IO drive level constrain

The IO drive level constrain specifies the drive level of a output signal .. if i am using LVCMOS33 with a drive level...

3 18yrs

kislo02

3 18yrs kislo02

Downloading external data file to FPGA

Hi I have a very basic question. Xilinx permits me to initialize Block RAM with an external data file. The thing I am j...

11 18yrs

FloXXX

11 18yrs FloXXX

Incremental compilation problem

Hi all, I am experimenting incremental compilation following the Quartus II software handbook. But somehow the fitter i...

2 18yrs

Tommy.Ai

2 18yrs Tommy.Ai

Xilinx XCL woes

OK, so I have this core I wrote which wants to read and write data to an= d = from SDRAM in a Spartan-E3 500 Microblaze...

1 18yrs

lists

1 18yrs lists

How to update a row and a column at the same clock cycle?

Hi I have a simple 4x4 array defined as follows: type rib is array (0 to 3) of std_logic_vector(3 downto 0); signal Ran...

2 18yrs

Hofman

2 18yrs Hofman

XILINX core generator question

Hi, Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to rea...

4 18yrs

Zorjak

4 18yrs Zorjak

Problem when for program and data memory use SDRAM

I have a PowerPC (Virtex2PRO) and SDRAM (programm and data memory). I anderstand that the bootloader may be use to load...

1 18yrs

axalay

1 18yrs axalay

using EXP connector of Spartan 3a board

We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We needed i/o pins to control motors and use various se...

3 18yrs

bisheshkh

3 18yrs bisheshkh

New Xilinx device package options for S3E & S3A

Thank you XILINX, you list new device package options for Spartan3E: (VQ100 for XC3S500E) http://www.xilinx.com/support...

2 18yrs

techseller

2 18yrs techseller

EDK 10.1 Map Error

Hi, Im getting the following error when trying to run the ML505 Standard IP Core Demo project from Xilinx. Im trying wi...

4 18yrs

raghunandan85

4 18yrs raghunandan85

XST 3.0 Xess Audio to Ethernet

Im a beginer in VHDL and i got some problems regarding Ethernet usage on XST 3.0 Board. I want to send audio trought et...

0 18yrs

pdrewa

0 18yrs pdrewa

Why this RLOC cannot be used two times?

Hi, I have encountered a strange problem. Because an adder is called many times by different width functions, I program...

0 18yrs

rxjwg98

0 18yrs rxjwg98

Xilinx LogicCore Direct Instantiation

Toolset: ISE/ModelSim_PE/VHDL I've been asked to modify one of my designs for another application so decided it was tim...

4 18yrs

krw

4 18yrs krw

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