Field-Programmable Gate Arrays

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CRC7 Input bits in Command and Response

Can someone confirm the SDIO CRC7 bits input for the 48 bits command and response and 136 response. For case 1 and 2 th...
1 comments posted 18yrs
posted by beky4kr
1 comments posted 18yrs posted by beky4kr

Microblaze Cache and FSL problem

Hi all , Out product uses the FSL bus to talk to a co-processor. So far I has the I and d cache for microblaze disabled...
0 comments posted 18yrs
posted by niladri1979
0 comments posted 18yrs posted by niladri1979

Video stream over bluetooth

Dear all, I need to transfer a live video stream from FPGA to let say a PC(Linux) , may you tell the design complexity...
3 comments posted 18yrs
posted by narendra.sisodiya
3 comments posted 18yrs posted by narendra.sisodiya

FPGA Programing file

I intend to build an fpga programer for the spartan fpgas of xilinx I am not sure about the file that i should send ove...
5 comments posted 18yrs
posted by cherin99
5 comments posted 18yrs posted by cherin99

incremental compilation

Hi all, I am experimenting incremental compilation on a design. But the logiclock region assignments are ignored and it...
0 comments posted 18yrs
posted by Tommy.Ai
0 comments posted 18yrs posted by Tommy.Ai

Xilinx EDK inferred dual port BRAM unconnected clkb

As part of an edk peripheral i have inferred 2 dual port BRAMs which synthesise and simulate correctly For both BRAMs p...
0 comments posted 18yrs
posted by godzillalad
0 comments posted 18yrs posted by godzillalad

HWICAP and BRAM

hi all, Iam trying to use HWICAP , as a first test i tried to write to HWICAP BRAM using XHwIcap_StorageBufferWrite and...
0 comments posted 18yrs
posted by fatma.abouelella
0 comments posted 18yrs posted by fatma.abouelella

Avalon interconnect fabric : arbiter

Hi all, I just have two simple questions but I can't find the answer from the altera's documents. Each master port has...
0 comments posted 18yrs
posted by charles.wagner
0 comments posted 18yrs posted by charles.wagner

URGENT :problem using Ethernet MAC ip core...

hello i am using a virtex 2 pro board to implement a communication system, and want to interface it with my pc (Matlab)...
1 comments posted 18yrs
posted by vikram788
1 comments posted 18yrs posted by vikram788

globals

I need some help with this one... Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP" (output signal=DONE_OBUF)...
2 comments posted 18yrs
posted by uraniumore235
2 comments posted 18yrs posted by uraniumore235

asic gate count

Hi, I am looking for some tool / ip that can give me approximate gate count of mapper/demapper. Any helpful hint is grea...
12 comments posted 18yrs
posted by vijayant.rutgers
12 comments posted 18yrs posted by vijayant.rutgers