signal value at power up

Try a Reset on Power up. For most FPGAs there is a global value for Powerup content that is valid before you use a reset. First of all, inspect the synthesis result. Only latches and FF are set during power up. All other signals depend on the contentg of Inputs, FF and latches.

bye Thomas

Thomas,

Thanks for your input. But what I was trying to figure out is that...If I am not using the reset, or not assign any values to signal, what happens in that case? I do know how to fix it but I was just curious to find out, why was this working for sometime but now doesn't work with a different part (same mfg)? Thanks, Martin

You *have* to assign a value to X or it won't simulate (properly) and it can't be constructed. X will always have a value 'U' and therefor so will Y. What is driving X? That determines the value of X at power up.

Rick

Power up period can be divided in to two parts,

1. Power up and before configuration starts -> This is dependent from FPGA to FPGA, most FPGAs tristate all the pins, hence the value will depend on how it is connected externally on board. Sometimes this also can depend on what voltage sequence that you are following to power up the FPGA.
2. During configuration -> Xilinx FPGA has a pin (I think HWSWAP) which determines at powerup how the pin should behave either pulled up or pulled low.

Hope this helps.

-- Goli

First, this will be optimized by synthesis to y

The normal synthesis result for the if clause would be y = x (wire). If x is never initialised, the wire could be removed and a FF driven by y won't be driven, so it could be removed, too. At any stage you will use the signal in a way, the synthesis stops removing and you might end with a FF without initialisation.

You should tell more about, what synthesis did with your code. The synthesis resulf for the code above may be not deterministic for different synthesis runs. But the only chance for the code above to have one programming file giving different results on different devices is IMHO a latch or FF without initialisation used in a technology that provides no defined state at power-up. You shoudl ask your vendor, wheter your technology provides defined states at power-up.

bye Thomas

=46rom the synthesis tool's perspective, the lack of any assignment to 'x' in the source code means that it is free to assign anything to 'x'. Furthermore, because 'y' depends on 'x' it means that the synthesis tool is free to assign anything to 'y' as well. There are five possibilities:

1. x set to '0' which implies that y will be assigned '0' as well.
2. x set to '1' which implies that y will be assigned '1' as well.
3. x connected to some existing signal in the design, which implies that y will track that signal as well.
4. y connected to some existing signal in the design.
5. y set to 'Z'.

If the synthesis tool chose #1 or #2, you wouldn't see any difference in the observable output 'y' as you change parts. Since that is not what you're observing it would rule out these choices.

If it implemented choice #3 or #4 then you'd have to back track further to see what is the power up state of the signal that it chose to connect to 'y'.

If it implemented choice #5 it might appear to power up differently with a different part because you'd be trying to discern a logic level from a signal that is not being actively driven.

In any case, the answer to your question lies in the equations file that was output from place and route. Take a look for the equations for output 'y' and the answer to the mystery will (most likely) be solved.

Kevin Jennings