Xilinx LogicCore Direct Instantiation

Any reason to not just infer the comparator? VHDL generics make this sort of thing a breeze.

Two things... First, I want to walk before running. I also need to manually instantiate BRAMs and it would be nice to ditch the GUI altogether. It would make managing mu libraries through various core releases much simpler.

Perhaps it's no longer true, but I found that the LogicCore devices were better optimized than the ones that were inferred from HDL. For equality, I'd just infer the thing and be done with it. Long magnitude comparators can have significant delays. At least that's what I've found in the past. (UPDATE: I did a test and inferred the comparators and one level up, even and it still seemed to pass timing (10% buffer through PAR) with the widest compare I expect (32 bits). Perhaps I'll go this way for the comparator anyway. It's simpler.)

I don't need generic for the inferred comparator (other than the ones describing the busses that are already there). ;-)

IMO it is good practice to infer first, while bearing this statement in mind. Then you have a portable design which may be largely good enough; you only need to pay attention to instantiation where the inferred design fails size or timing (which does still happen sometimes)

Sounds as if the comparators are good enough now.

- Brian

Perhaps, but I never know what will be asked next (portability will not). I'd like to have as robust of a design as possible out of the box, since I won't be around to pick up the pieces.

The comparators are good enough and I think I know how to make them faster, if need be. This doesn't do the BRAMs any good though. They're still going to be a PITA.