OK, so I have this core I wrote which wants to read and write data to an= d =
from SDRAM in a Spartan-E3 500 Microblaze system. There will be quite a lot of data moving around, and also I want the thi= ng =
to be self-serving, not need to call the CPU to make a request to =
opb_central_dma, so I connected it to the mch_opb_sdram controller using= =
one of the MCH/XCL channels, not on the OPB bus. There will be another =
core with the same interface, the SDRAM acting like a large FIFO between= =
the two (and also storing microblaze code and data).
Anyway, it looks good in ISE simulator (simulating only my core) and the= n =
in the FPGA it fails. The SDRAM controller locks up and doen't respond =
even to the CPU. That is a small problem, I must have done something wro= ng =
;)
I'm using EDK 9.1i
With ChipScope, this is the thing trying to emit a XCL Write transaction= :
Note that here it emits to the FIFO every 2 clock cycles. Is this a =
problem ? Can the SDRAM controller stall ?
- It emits a 32-bit address on the MCH_data lines, which is actyally =
address 0
- Control is set to 1 to indicate a write transaction
- Write is set to 1 to push it in the FIFO
- Cacheline size is set to 4 (which I hope is 4 words ?) so the core emi= ts =
4 32-bit datums, setting Control to 0 and pulsing Write each time
- The core now wants to write another burst so it emits again the addres= s =
(this time 0x10), sets Control to 1 ans pulses Write
- FIFO is full so it waits forever.
Apparently the mcb sdram controller isn't reading from the other side of= =
the FIFO...
Now this is the thing trying to emit a XCL Read transaction :
It emits 4 read commands (address + control=3D0 + pulse Write). Thet it waits for read data that never comes.
Soooooo..... there isn't much documentation on this subject it seems ;) If anybody has information, I would be very, very happy !!!!
Thanks ;)