Hi,
Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001?
This document
formatting link
shows that the older version, XST 5.x, has partial support for Verilog
2001.
I was wondering if the support is better in the newer version of ISE.
In particular, I'm interested in knowing if 'generate' works, and whether arrays of instances work. The latter was actually added to the language in 1995, but XST 5.x doesn't seem to support it.
Regards, Allan.