Does Xilinx XST plan on supporting `define macro( X ) ?

I've downloaded the Webpack 6.3, and found that XST still lacks support for Verilog define-arguments.

`define MINIMUM2( x, y ) ( ((x)>(y)) ? (y) : (x) )

parameter IN_BUS = 16; parameter OUT_BUS = 8;

parameter DATA_BUS = `MINIMUM2( IN_BUS, OUT_BUS );

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If I try to synthesize this, Xilinx gives me a strange syntax error. It's obviously stumped by my `define macro. Thankfully, I rarely use these constructs in RTL-code, but it's convenient for certain expressions and bit-manipulations.

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And support for the system-tasks $signed() and $unsigned() would be nice, too!