Hi,
Does anyone know if XST 6.1.3 supports the "indexed part select" feature of Verilog 2001? (It's in section 4.2.1 of the LRM.)
The Xilinx documentation states explicitly that it does support this feature, yet when I try to use it, I get this error message:
ERROR:Xst:850 - foo.v line 134: Unsupported .
Example code:
reg [7:0] bar; wire [31:0] foo;
genvar j; generate for (j=0; j
The Xilinx support guy suggested this (inappropriate) code as a workaround, then closed the case before I'd had a chance to respond. :(
module test_module(bar,foo,clk);
output [31:0] bar; input [31:0] foo; input clk;
reg [31:0] bar ; wire [31:0] foo ;
genvar j;
generate for (j = 0 ; j < 8 ; j = j + 1) begin : label always @ (posedge clk) bar[j]
Allan,
I believe that the code you referenced is called "Vector bit-select and part-select addressing". The XST User Guide does state support of "Array bit-select and part-select" which I believe is different than the code you mentioned below. XST does not support the addressing scheme
[4*j +: 4]that you mentioned.
best regards
Steve
Allan Herriman wrote:
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