How to use a generic memory with Xilinx ?

Question

Hello allI am struggling with ISE and CoreGen to generate a memory block thatwould be customizable (mainly in depth & width) through genericparameters.The Memory block generator datasheet seems to indicate that this ispossible but does not explain how. All there is is the parameterslist.ISE keeps telling me "Port  of instance  hasdifferent type in definition "I don't have any component named blk_mem (I had generated one with theGUI but I have deleted it and removed from ISE project)Thanks in advanceNicolas

sudhi · Accepted Answer

Memory blocks generated using CoreGen will have fixed widths and depth. The VHDL file generated is only for simulation (Using XilinxCoreLib) and the actual implementation is in the EDIF file. The EDIF file is used by ISE during synthesis.

One way to get configurable memory using generics is to let the synthesis tool (XST, Leonardo Spectrum etc.) infer block ram from VHDL code.

Here is a link which may be useful

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Hope this helps.

-Sudheendra Kadri

Darol Klawetter · Answer

The Xilinx XST documentation will provide the HDL coding structureneeded to infer various RAM types. You don't necessarily need to usethe LogicCore generator for RAM.Darol Klawetter

How to use a generic memory with Xilinx ?

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