How to use a generic memory with Xilinx ?

Hello all I am struggling with ISE and CoreGen to generate a memory block that would be customizable (mainly in depth & width) through generic parameters. The Memory block generator datasheet seems to indicate that this is possible but does not explain how. All there is is the parameters list.

ISE keeps telling me "Port of instance has different type in definition " I don't have any component named blk_mem (I had generated one with the GUI but I have deleted it and removed from ISE project)

Thanks in advance Nicolas

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Nicolas Matringe
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Memory blocks generated using CoreGen will have fixed widths and depth. The VHDL file generated is only for simulation (Using XilinxCoreLib) and the actual implementation is in the EDIF file. The EDIF file is used by ISE during synthesis.

One way to get configurable memory using generics is to let the synthesis tool (XST, Leonardo Spectrum etc.) infer block ram from VHDL code.

Here is a link which may be useful

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Hope this helps.

-Sudheendra Kadri

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The Xilinx XST documentation will provide the HDL coding structure needed to infer various RAM types. You don't necessarily need to use the LogicCore generator for RAM.

Darol Klawetter

Reply to
Darol Klawetter

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