Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001? If so, what was the first version to support it? I'm mainly looking at support for 'signed' number support. (Signed regs, wires, inputs/outputs, and '>>>')
Xilinx Webpack ISE and Verilog-2001?
Aug 09, 2003
1 Replies
First reply
Following link shows 2001 support on 5.1i ISE and later. This information is extracted from the ISE software manual guide. Regards, Wei =========================================================== Verilog 2001 Support in XST XST now supports the following Verilog 2001 features.…
Read the full replyFollowing link shows 2001 support on 5.1i ISE and later.
formatting link
This information is extracted from the ISE software manual guide.
formatting link
Regards, Wei
=========================================================== Verilog 2001 Support in XST
XST now supports the following Verilog 2001 features. For details on Verilog 2001, see Verilog-2001: A Guide to the New Features by Stuart Sutherland, or IEEE Standard Verilog Hardware Description Language manual, (IEEE Standard 1364-2001).
- Comb> Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001? If so, what
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