Setting VHDL standard in Xilinx ISE

Hi

Does anyone here know, how to explicitly set which VHDL standard should be used by Xilinx ISE (actually, by XST I think)?

Cheers Wojtek

Reply to
wojt
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Wojtek,

The XST Users Guide gives specific details on which VHDL standard XST supports (and those that are conflicts). See the UG located here:

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I do not believe that there is a way to specify the exact standard that you may want to use. Verilog 2001 appears to be the only HDL standard that is selectable within the synthesis options.

-David

Reply to
davide

David, Not have a setting is real bad.

Last I looked Xilinx's recommended coding styles for coding multiple edge FIFOs uses VHDL-93 shared variables. In VHDL-2002 (the current IEEE revision) shared variables require protected types. Hence Xlinx's coding methodology is illegal in the current standard.

Without a switch, what is going to happen to that code that functions just fine, but is illegal?

BTW there are 1076.6-2004 recommended coding styles for this structure (a single process with 2 clock edges). I haven't checked recently, does Xilinx support them.

Cheers, Jim

Reply to
Jim Lewis

Hi Jim,

I have been reviewing the XST VHDL IEEE support documentation and there is no mention of 1076-2002 support. XST does support 1076-1987, 1076-1993 and a partial implementation of 1076-2006. Might there be some revision from the 2002 to the 2006 spec in regards to shared variables? I don't know.

What I read about shared variables for BRAMs with two write ports stated: "The XST VHDL analyzer accepts shared variables, but errors out in the HDL Synthesis step if a shared variable does not describe a valid RAM macro."

Now everybodys interpretation is going to be different, but the wording 'accepts shared variables' seems to be a coding option rather than hard fast rule. On the other hand, the VHDL code example specifically uses shared variable syntax (as a general example).

I would recommend that you (and any other engineer) looking to have a VHDL switch option to open a case with Technical Support and ask for an enhancement request to XST.

-David

Reply to
davide

You don't.

XST doesn't care whether it's compiling VHDL or Verilog. You can happily intermix them in the same project.

G.

Reply to
ghelbig

You don't.

XST doesn't care whether it's compiling VHDL or Verilog. You can happily intermix them in the same project."

The person who posted with snipped-for-privacy@lycos.com in a From field missed the point: the point is not about Verilog and VHDL; but about choosing between different versions of VHDL (dated 1987; 1993; 2002; and 2006). XST does not have a way to allow a user to select one of these in particular from a selection of at least two options. This is in contrast to other vendors' tools. E.g. ncvhdl:

05.70-s005: (c) Copyright 1995-2006 Cadence Design Systems, Inc., which has a mode intended for VHDL87; another mode intended to "Enable VHDL93 features"; and the -V200X command line switch (which has no graphical counterpart in the NCLaunch GUI) to "Enable VHDL200X and VHDL93 features". Another example, from the "Version Y-2006.06 HDL Compiler (Presto VHDL) Reference Manual": "[..] The VHDL language is specified in IEEE 1076, which is updated continually, with IEEE 1076-1993 being the most recent revision[sic, this is from documentation from Synopsys dated May 2006]. To support these updates and provide other improvements, Synopsys developed the HDL Compiler (Presto VHDL) tool, which is described in this manual and turned on by default. The original VHDL Compiler is described in the HDL Compiler for VHDL Reference Manual.

For a list of supported VHDL-93 features, [..] Table 7-4 Variables Name Default Description [..] hdlin_vhdl_87 False When true, directs Presto VHDL to use the VHDL-87 standard. [..]"

For XST, one's code may be treated as VHDL93 or VHDL87 but the choice is made by XST while it examines the code instead of by a user or enforced company policy, from

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: "[..] VHDL IEEE Conflicts VHDL IEEE std 1076-1987 constructs are accepted if they do not conflict with VHDL IEEE std 1076-1993. In case of a conflict, VHDL IEEE Std 1076-1993 behavior overrides VHDL IEEE std 1076-1987. In cases where: . VHDL IEEE std 1076-1993 requires a construct to be an erroneous case, but . VHDL IEEE std 1076-1987 accepts it, XST issues a warning instead of an error. (An error would stop analysis.) [..]"

Regards, Colin Paul Gloster

Reply to
Colin Paul Gloster

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