I was trying to use a macro 'expression' --
`define MAXIMUM2( x, y ) ( ((x)>(y))?(x):(y) ) // return greater value
parameter A_W = 10; // Abus width (#bits) parameter B_W = 12; // Bbus width (#bits) parameter C_W = `MAXIMUM2( A_W, B_W ); // Cbus: intersect(A_W, B_W)
This works in NC-Verilog 4.0, Modelsim 5.6, Design Compiler 2003.06, and Ambit/PKS 5.0. Xilinx ISE 6.1i's "XST" doesn't like it. Overall, so far so good!
Then I tried to get more clever ...
`define MAXIMUM3(x,y,z ) ( (`MAXIMUM2(x,y)>z) ? (`MAXIMUM2(x,y)):(z) )
This barfs on most of the above...
Do any Verilog tools support nested MACROs?
('common, C-programmers have been doing this sort of #define stuff for ages!)
Also don't worry...I'm not using the MACROs to evaluate combinational exprsesions. I use the MACROs in parameter definitions. (I have some data-bus width conversions in a few datapath modules. Each 'node' needs to be sized to the larger of the 2 endpoints.)