I'm trying to run the Xilinx toolset from the MS-DOS command prompt. Ultimatly I plan to do all of my VHDL design in Linux using WINE, but before I do that I want to get the commands working in MS-DOS. The Xilinx software I'm using is ISE 4.2i. For the first test I have created the following VHDL code (called source.vhd):
/********************************************/ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity source is Port ( a : in std_logic; b : out std_logic ); end source;
The document you should be referencing to learn about command line tools and their options is the Development System Reference Guide for ISE 4.x found here:
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This document will cover the overview, syntax, inputs, outputs, and options for the command line tools you are using as well as some others you may need.
XST command line usage is covered in the XST User Guide for ISE 4.x found here:
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See Chapter 8 for more info on using XST command line mode.
The command to include a ucf constraint file is ngdbuild -uc yourfile.ucf yourdesign.ngd To know if your ucf file has been taken into account, look in the translate(ngdbuild) report (*.bld).
To know the tools and the options you can look in the software manual and then development system reference guide. For XST it is the software manual and then XST User Guide. FYI the -f file.rsp option is to use a file to write your options in it. For example your could write your par line like: par -ol 2 -xe 0 -t 1 etc... And you could put all the commands in a batch file (you might have done it already). however I recommend you to try each command line on its own first and the group them in batch files. For example translate and map in the same batch. You can also create different batch file for different implementation options. Command line is very good to put files in different directories or give a different name to output file (for example the ouput of par (*.ncd) with a different name to avoid the confusion with the map output).
My suggestion is to rename your UCF file the same name as your top level source. If your top-level source is source.vhd, then your UCF should be source.ucf. Then I suggest using xflow to run the tools from command-line. It is likely much easier than the path you are attempting to take now. For instance to make the run it appears you are attempting below, the following command-line should take care of that:
Note: The above command-line is for 4.1/4.2i, it might be a little different for different releases. The prj file lists all of the VHDL designs in your project. Take a look at the docs or the one in your GUI runs you have already done if you want to see the format.
You can customize your flow further if you wish and you can use the resulting bat file from the run if you prefer however I generally suggest removing the xflow.bat file and re-executing xflow each time as it will then better adjust to any future changes you would decide to make to how the design is implemented.
Generally, for those that want to run the Xilinx tools from command-line, i highly suggest using Xflow. It has quite a few advantages over most other methods, especially when you are just starting out with learning the tools.
Why are you using 4.2? 6.2 is Linux native. Also there is no XST in 4.2, you need 6.x for that (the 5.x version didn't work very well, the current version works fine). If you are planning on working in a Linux environment eventually then install cygwin on your Windows machine. That will allow you to use the same shells as Linux. I've included a complete set of csh scripts for running the Xilinx tools in HDLmaker,
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Look under hdlmaker_lib/csh, you'll find a number of useful csh scripts.
If you use HDLmaker to build your hierarchy it will generate all of the constraint files that you need including a script for XST and the UCF file. HDLmaker works best in Verilog, the VHDL support has been deprecated. It's been 6 or 7 years since any of my clients have wanted VHDL, every company that I deal with uses Verilog. As a result I haven't been maintaining the VHDL generators in HDLmaker, all of the work has gone into Verilog. HDLmaker runs fine under Cygwin and of course it works on all *nixs.
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