Very Stupid XST verilog synthesis question...

See

Ahh, all so simple!

Just use an assignment when you define the reg. Initial blocks are ignored as for synthesis only.

HTH,

Mike

module test_reg ( clk_0, live_pulse, live_lag, live_lag2, live_lag3, live_lag4 );

input live_pulse, clk_0;

output reg live_lag, live_lag2, live_lag3 = 1'b0, live_lag4 = 1'b0;

always @(posedge clk_0) begin live_lag XST's (6.1) verilog synthesizer for inferred registers (target V2pro):

analyzer.

This

be

register

in

V2pro):

analyzer.

This

be

"It is illegal to attach INIT to a net or signal in FPGAs."

You could instantiate an FD for live_lag3 and live_lag4 and apply the INIT constraint to each flop, or instantiate FDC for each signal even though the clear input of the FDC is set to 1'b0 it will come up low.

I generally add a clear input to my lower level modules and a reset term in my clocked processes like:

module foo (live_pulse, clear, clk, live_lag); input live_pulse, clear, clk; output live_lag; always @ (posedge clk or posedge clear) if (clear) live_lag

register