OK. I'm just braindead, my verilog is horribly rusty, insert tons o excuses here, but...
I'm struggling with how the initial condition semantics are working in XST's (6.1) verilog synthesizer for inferred registers (target V2pro):
All this is being tested by compiling and viewing with a logic analyzer.
live_pulse is an input which goes high for a single clock cycle. This is a gross hack upstream, but I got that to work.
But given that, I'm having trouble defining initial conditions for inferred registers. I don't want to wrap everything in a big reset statement that is unnecessary, given that I'm not going to port this to an ASIC so I'm perfectly happy with assuming "all registers shalt start at 0"
The sample code:
reg live_lag, live_lag2, live_lag3, live_lag4; // synthesis attribute INIT of live_lag3 is "R" always @(posedge clk_0) begin live_lag