Very Stupid XST verilog synthesis question...

OK. I'm just braindead, my verilog is horribly rusty, insert tons o excuses here, but...

I'm struggling with how the initial condition semantics are working in XST's (6.1) verilog synthesizer for inferred registers (target V2pro):

All this is being tested by compiling and viewing with a logic analyzer.

live_pulse is an input which goes high for a single clock cycle. This is a gross hack upstream, but I got that to work.

But given that, I'm having trouble defining initial conditions for inferred registers. I don't want to wrap everything in a big reset statement that is unnecessary, given that I'm not going to port this to an ASIC so I'm perfectly happy with assuming "all registers shalt start at 0"

The sample code:

reg live_lag, live_lag2, live_lag3, live_lag4; // synthesis attribute INIT of live_lag3 is "R" always @(posedge clk_0) begin live_lag

Reply to
Nicholas Weaver
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See

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(or the same thing at
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) for the information on Initial Value support in Verilog2001.

Reply to
John_H

Ahh, all so simple!

--
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply to
Nicholas Weaver

Just use an assignment when you define the reg. Initial blocks are ignored as for synthesis only.

HTH,

Mike

module test_reg ( clk_0, live_pulse, live_lag, live_lag2, live_lag3, live_lag4 );

input live_pulse, clk_0;

output reg live_lag, live_lag2, live_lag3 = 1'b0, live_lag4 = 1'b0;

always @(posedge clk_0) begin live_lag XST's (6.1) verilog synthesizer for inferred registers (target V2pro):

analyzer.

This

be

register

Reply to
mike.peattie

in

V2pro):

analyzer.

This

be

"It is illegal to attach INIT to a net or signal in FPGAs."

You could instantiate an FD for live_lag3 and live_lag4 and apply the INIT constraint to each flop, or instantiate FDC for each signal even though the clear input of the FDC is set to 1'b0 it will come up low.

I generally add a clear input to my lower level modules and a reset term in my clocked processes like:

module foo (live_pulse, clear, clk, live_lag); input live_pulse, clear, clk; output live_lag; always @ (posedge clk or posedge clear) if (clear) live_lag

register

Reply to
Gabor

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