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Relative placement constraints in Xilinx ISE w/ Verilog

I am building a design which consists of a two-dimensional array of smalll processing elements, each of which contains about 60 LUTs. The two dimensional array is constructed in Verilog by creating a "column" module which contains instances all of the PEs in a column An "array" module then puts together the columns.

I would like to create placement constraints to make the placer follow the array structure. So I dug around in the documentation and found "RLOC", which sounds like it specifies what I want. So I added constraints to each column array that look something like this:

module PE_column(blah blah)

PE_instance C0(blah blah blah); // synthesis attribute RLOC of C0 is "x0y0"

PE_instance C1(blah blah blah); // synthesis attribute RLOC of C1 is "x0y1"

etc.

endmodule

I tried something similar with to place the columns at X0y0, x1y0, etc. at the next level up in the hierarchy.

When I run XST, it dutifully reports the constraints, but the placer apparently ignores them.

If someone could point out what I'm missing, I'd really appreciate it. Is it necessary to make the lower-level instances RPMs? If so, what is the (currently) easiest way to do this?

BTW I am using XST in ISE 7.1.03I compiling to a Xc2v6000.

Thanks!

John Nestor Lafayette College

Reply to
nestorj
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The RLOCs only apply to primitives, and hierarchical levels below with RLOCs on the primitives. In other words, they have to be put on the elements that are actually used in the FPGA. So yes, the lower level instances must also be RPMs, all the way down to the the primitive level.

You may be able to use an area constraint for what you are asking to do.

Reply to
Ray Andraka

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