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XST and Verilog $readmemh

In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion.

I look at the .syr output file from XST, and it claims to have read the file. But...

If I hook a logic analyzer up to the output of the memory, it looks like it never got initialized.

Another problem I'm seeing is that XST appears to not like having an address line (@000) in the file. Also, if the the file is too short, XST complains and discards the initialization.

I'll dig into this some more, but I was wondering if anyone had had any success with this.

Thanks!

John Providenza

Reply to
johnp
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Here's some more info... In the .syr report file from XST, I see the lines:

INFO:Xst:2546 - "C:/usr/JOHNP/mentor/enet/hw/pblaze_rtl/../rtl/ pblaze.v" line 84: reading initialization file "../sim/foo.memh".

but later...

WARNING:Xst:1781 - Signal is used but never assigned. Tied to default value.

This explains why I get 0's from the memory - it's been optimised out and tied to 0.

Any ideas for simple work-arounds? I've opened a WebCase, but my expectations from them are realistic, ie, very low.

John Providenza

Reply to
johnp

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