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Xilinx FPGA Clock Skew

Hi,

In FPGA we can't control over the clock skew since it is being routed via dedicated lines.

When i am looking in to the timing reports, Some times i am getting the Clock Skew value as 0.102ns.. ie., in Positive

And some times, -0.123 ie., in Negative.

Actually,How the timing report tells the clock skew?

How it is being measured?

Regards, Muthu

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Muthu
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