Clock delay vs. clock skew

Clock delay is the time elapsed between sending the clock and its arrival at a specific destination. Clock skew is the difference in arrival time at different destinations.

Larger chips unavoidably have a longer clock delay. That's why DLLs, DCMs and PLLs are so important, for they can reduce the clock delay to zero, completely eliminating it. Clock skew cannot be reduced by DLLs and PLLs, it can only be minimized by careful clock routing structures and generous buffering. Excessive clock skew can lead to hold-time problems or to reduced performance, depending on the direction of the clock delay difference. If the clock is delayed in the direction of the data flow, there is the danger of hold-time violation. It the clock is delayed in the opposite direction, max performance is reduced. Modern FPGAs try to keep clock skew below a few hundred picoseconds. Peter Alfke

So, this is outside the chip, that the clock is send? The delay is generated by the input buffer IBUFG?

Both internal and external - but if including an output-delay, this is both skew and delay?

about clock delay on the board, and clock skew on the board, the same rules apply. On the board, clocks are usually not re-buffered, and clock delay and skew are usually determined by the propagation velocity, which is roughly half the speed of light. Clock delay and skew are, therefore, of the same order od magnitude. On-chip, the clock goes through many buffering stages, which makes the delay long, but can keep the skew quite small, only a few % of the delay.

IBUFG is just one contributor to clock delay, then there is the whole clock distribution network.

Just remember: delay is from source to destination, skew is between destinations. Peter Alfke

I believe what you explained above is correct.

I have one confusion on the Xilinx "place and route" timing report. I got a timing result (a skewtest module using Xilinx spartan III - XC3S1000FG320) like this:

----------------------------------------------------------------------- Slack: -0.659ns CLKEXT Error: 0.759ns skew exceeds 0.100ns timing constraint by 0.659ns

Skew(ns) DCM_X0Y1.CLK0 V2.O1 3.608

0.745 DCM_X0Y1.CLK0 T5.O1 3.587 0.724 DCM_X0Y1.CLK0 V3.O1 3.579 0.716 DCM_X0Y1.CLK0 T4.O1 3.622 0.759

------------------------------------------------------------------------

I can understand that the 3.608ns is the delay from DCM_X0Y1.CLK0 to V2.01. I don't know what 0.745ns skew stands for, since there is only ONE destination (V2.01). Can you shed some light on?

Thank you in advance.

Regards,

Jane DSP System Engineer