Xilinx clock net skew vs. MAXSKEW

Here's the situation: an external signal is used as a local clock for a set of eight IOB FFs. There is a UCF file MAXSKEW constraint of

70ps on the signal. PAR reports very low skew (~20ps) on the clock net. However, the MAXSKEW constraint is shown as violated (~200ps skew).

I was surprised b/c in an earlier design w/ local clocking for CLB FFs, the net skew and MAXSKEW values only differed by about 40ps.

Does anyone have insight as to what contributes to the additional skew when clocking at IOB FFs?

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