clock skew problems

Hi all,

I've got a FPGA design with a lot of clocks! I know this is not really good, but I've to implement a microprocessor initially designed for an ASIC. The microprocessor uses combinatorial signals to drive latchs and Flipflops.

I tried to re-clock some critical signals with a faster clock but this is not very efficient.. :-( and I've trouble with this clock, ISE gives me warnings : Route:447 - CLK Net : my_clock may have excessive skew because 2 NON- CLK pins failed to route using a CLK template. ( I've this warning for a lot of others clock generated by combinatorial logics... )

My question is how can I locate the 2 NON-CLK pins ? because I've a fanout of 678 signals... and if I've to search manually, it could be very long! Is there an ISE functionality to do that ?

Thanks by advance,

Best regards, Michel.

Reply to
michel.talon
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You probably know the design well enough to guess where these loads are. Are you creating a gated clock somewhere? Does this clock drive an output pin? Any flip-flop in the design using the clock will "route using a CLK template", so gates (LUTs) and pins (IOBs) and possibly clock muxes (BUFGMUX) or DCM's will be the problem loads.

By the way, skew is only a problem if the loads mentioned actually drive some synchronous logic. For example gated clocks used by flip-flops receiving inputs from the original clock domain. The "excessive skew" doesn't apply to the other 676 clock loads tha do "route using a CLK template."

HTH, Gabor

Reply to
Gabor

Use FPGA Editor to open the routed design. Find the clock net and highlight it. Press F2, or select Edit -> Properties of Selected Items... Choose the 'Pins' tab. You will see a list of all the pins on that net. Scroll down the list until you find pins that don't have .CLK (or some variant like .ICLK1 or .CLKA) in their name.

--
Joe Samson
Pixel Velocity
Reply to
Joseph Samson

Hi,

I found the pin list, and all pins are named like .ICLK The two pins which have a different name are inputs of two BUFGMUX. It seems to be matching with my ISE warning ( my_clock may have excessive skew because 2 NON-CLK pins failed to route using a CLK template ). But there is something I don't understand.. I used BUFGMUX primitive to avoid clock problems and to keep my_clock on the global clock network. Does it mean that I can't connect a clock on a BUFGMUX input ? so, how can I do to multiplex clocks keeping my_clock on a global clock network to avoid skew problems ?

Thanks by advance,

Best regards, Michel.

Reply to
michel.talon

The input to a BUFGMUX is not on the global clock trees. Normally it would be fed by standard routing if the clock is generated inside the FPGA, or dedicated routing from a DCM or a global clock input buffer. In any case the BUFGMUX itself has a significant delay and therefore it is not reasonable to expect the output of a BUFGMUX to have low skew compared to its input. If you need the multiplexed clocks to have low skew compared with a non-multiplexed clock, you need to place the same signals on the BUFG and BUFGMUX inputs, and you need to use BUFG and BUFGMUX on the same edge of the chip. Generally there is no problem routing dedicated clock sources to more than one BUFGMUX. The FPGA editor can give you a better view of the routing and timing.

HTH, Gabor

Reply to
Gabor

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