I've got a FPGA design with a lot of clocks! I know this is not really good, but I've to implement a microprocessor initially designed for an ASIC. The microprocessor uses combinatorial signals to drive latchs and Flipflops.
I tried to re-clock some critical signals with a faster clock but this is not very efficient.. :-( and I've trouble with this clock, ISE gives me warnings : Route:447 - CLK Net : my_clock may have excessive skew because 2 NON- CLK pins failed to route using a CLK template. ( I've this warning for a lot of others clock generated by combinatorial logics... )
My question is how can I locate the 2 NON-CLK pins ? because I've a fanout of 678 signals... and if I've to search manually, it could be very long! Is there an ISE functionality to do that ?
Thanks by advance,
Best regards, Michel.