Dear all,
In ASIC design, clock skew can be solved by using Clock tree generation. How does FPGA solve it?Use the clock tree too?How?
Thanks,
Ethan
Clock skew in FPGA Xilinx?
Aug 27, 2005
2 Replies
In FPGAs the clock tree is already in the design. You don't have to do anything extra to use it as long as you feed the clock into the clock tree correctly. This alas precludes interesting clock manipulation tricks like clock gating etc except at a very global level.
the clock tree in FPGA is already there, but the tool automatically places and routes the resources while taking into account the clock tree skew.
Vladislav
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