hi all,
i have no of D flip flops cascaded now there are two ways clock can be routed.
1) in the direction of the data flow. 2) opposite to the direction of the data flow.which of the above is good??
thanks in advance
rgds, praveen
Opposite direction will maximise hold time, which is probably what you need.
But this is not an FPGA question. In an FPGA you probably have no choice about clock routing - it's done for you by the dedicated clock networks.
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Good question, Praveen. Since 1988, every young engineer that I interviewed for employment here at Xilinx ( i.e. a couple of hundred) had to come up with an answer to that question.
If you have a choice ( in an FPGA you should use global clocks, so you have no measurable delay difference anyhow) there is a trade-off:
Running the clock against the data flow sacrifices performance by increasing the set-up time, but it is the safeest method, and therefore recommended.
Running the clock in the direction of the data flow reduces set-up time and thus alllows a higher clock rate, but changes the input requirements in the direction of a positive (or more positive) hold time. If overdone, this can create a race condition, and "failure at any clock speed". Therefore not recommended.
Peter Alfke, Xilinx Applications
routed.
recommended.
routed.
recommended.
Hi Peter,
Yes. I too clear with this.
I have one question regarding clock skew.
As you said, In FPGA we can't control over the clock skew since it is being routed via dedicated lines.
When i am looking in to the timing reports, Some times i am getting the Clock Skew value as 0.102ns.. ie., in Positive
And some times, -0.123 ie., in Negative.
Actually, what it means.??? How the timing report tells the clock skew?
How it is being measured?
Regards, Muthu
routed.
recommended.
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