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How to handle clock skew?

In an FPGA design with an Altera ACEX and Quartus II I get clock skew.

There are data paths between several modules and a derived 64 MHz master clock. Adding or changing the design in another part of the design leads to a change or the distance of the data paths of the modules.

As a result there is always the possibility of incorrect circuit functionality due to clock skew.

The Quartus Handbook says in the chapter Advanced Timing Analysis: "... This is achieved by adding cells to the path or through the placement of the source and destination registers."

Conclusion: (1) If adding or changing the design I have to control the clock skews and therefore place lcells into the data paths EVERY compiler run (2) Place the source and destination registers by hand on the layout? This is not possible in the ACEX ...

Is this really the way to make a good FPGA design or am I missing something in the assignments or timing requirements?

Thanks for any help.

/Alois

Reply to
Alois Huber
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Maybe your clock isn't on one of the global clock networks.

-- Mike Treseler

Reply to
Mike Treseler

You could use the clocklock feature to de-skew the clock input to the register.

Reply to
Jezwold

Sure, and that is one reason why static timing analysis tools hav

been created. If you constrain your clock paths using the timin analyzer, you can sets requirements on the skew so that the tool either route the clocks well, or fail with timing errors. Look int the Quartus documentation for how to actually implement this

Also, depending on the part you are using, you probably have a PL

available, as well as global clock nets, which will do an excellen job of generating a low-skew global clock

Reply to
pdq

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