In an FPGA design with an Altera ACEX and Quartus II I get clock skew.
There are data paths between several modules and a derived 64 MHz master clock. Adding or changing the design in another part of the design leads to a change or the distance of the data paths of the modules.
As a result there is always the possibility of incorrect circuit functionality due to clock skew.
The Quartus Handbook says in the chapter Advanced Timing Analysis: "... This is achieved by adding cells to the path or through the placement of the source and destination registers."
Conclusion: (1) If adding or changing the design I have to control the clock skews and therefore place lcells into the data paths EVERY compiler run (2) Place the source and destination registers by hand on the layout? This is not possible in the ACEX ...
Is this really the way to make a good FPGA design or am I missing something in the assignments or timing requirements?
Thanks for any help.